Technical Program

April, 9th

Tutorial #1 – Mixed-signal DFT & BIST: Trends, Principles, and Solutions

Room: Pompeian III
Time: 08:30 – 12:00
Presenter: Stephen Sunter (Mentor Graphics)

Tutorial #2 – Automotive Reliability & Test Strategies

Room: Pompeian III
Time: 13:00 – 16:30
Presenter: Yervant Zorian (Synopsys)

April, 10th

Registration & Breakfast

Time: 07:30 – 08:30

Plenary Session

Room: Pompeian I/II
Time: 08:30 – 10:30

  • Welcome Message – Yiorgos Makris (U.T. Dallas), General Chair
  • Program Introduction – Srivaths Ravi (Texas Instruments), and Amit Majumdar (Xilinx), Program Co-Chairs
  • Opening keynote
    Dr. Ahmad Bahai, (CTO, Texas Instruments)
  • Keynote tribute to Professor Mel Breuer – Contributions to CAD and Test
    Organizer: Sandeep Gupta, Univ. of Southern California
    Miron Abramovici, Miron PhotoArt
    Magdy Abadir, Helic Inc.
    Sridhar Narayanan, Apple Inc.

1A – Analog, Mixed-Signal and RF Test (I)

Room: Pompeian I
Time: 11:10 – 12:10
Moderator: Stephen Sunter (Mentor Graphics)

  • A Technique for Dynamic Range Improvement of Intermodulation Distortion Products for an Interpolating DAC-based Arbitrary Waveform Generator Using a Phase Switching Algorithm
    Peter Sarson (ams AG), Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi (Gunma University)
  • [Best Paper Nominee] Accurate Jitter Decomposition in High-Speed Links
    Yan Duan (Iowa State University), Degang Chen (Iowa State University)
  • Adaptive test flow for mixed-signal ICs
    Haralampos Stratigopoulos (Sorbonne Universités, UPMC Univ. Paris 6, CNRS, LIP6), Christian Streitwieser (ams AG)

1B – Delay & Performance Test

Room: Pompeian II
Time: 11:10 – 12:10
Moderator: Purna Mohanty (Tessolve)

  • A New Delay Testing Signal Scheme Robust to Power Distribution Network Impedance Variation
    Claude Thibeault, Ali Louati (E. Tech. Sup. Montreal)
  • Aging Monitor Reuse for Small Delay Fault Testing
    Chang Liu (university of stuttgart), Michael Kochte, Hans-Joachim Wunderlich (University of Stuttgart)
  • An Optimised SDD ATPG and SDQL Computation Method Across Different Pattern Sets
    Wilson Pradeep (Texas Instruments), Prakash Narayanan (Texas Instruments India Pvt. Ltd), Rubin Parekhji (Texas Instruments (India))

1C – IP Session: Screening for Layout Sensitive Defects

Room: Pompeian III
Time: 11:10 – 12:10
Organizers & Moderators:Arani Sinha, Nitin Chaudhary (Intel Corporation)

  • Fast yield learning method using correlation of manufacturing defects on circuits based on DFM rule check
    Tapan Chakraborty (Qualcomm)
  • Screening Yield Systematics Through Holistic Volume Diagnosis in a Leading-edge Foundry
    Yan Pan (Global Foundries)
  • Physical pattern analysis to identify test escape risks
    Ya-Chieh Lai (Cadence Design Systems)

Lunch break – a word from our Elite Supporters

Time: 12:30 – 13:30

  • Tessolve, speaker: Purna Mohanty
  • ams AG, speaker: Peter Sarson

2A – ATPG (I)

Room: Pompeian I
Time: 13:40 – 14:40
Moderator: Loganathan Lingappan (Intel Corporation)

  • Fail Data Reduction for Diagnosis of Scan Chain Faults under Transparent-Scan
    Irith Pomeranz (Purdue University)
  • [Best Paper Nominee] Methodology of Generating Dual-Cell-Aware Tests
    Yu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien (National Chiao Tung University), Ying-Yen Chen, Max Wu, Jih-Nung Lee (Realtek Semiconductor Corp.), Mango Chao (National Chiao Tung University)
  • Test-Set Reordering for Improving Diagnosability
    Cheng Xue, Ronald Blanton (Carnegie Mellon University)

2B – New Topic: Innovation for Emerging Smart IoT Systems

Room: Pompeian II
Time: 13:40 – 14:40
Organizer/Moderator: Bozena Kaminska (Simon Fraser University) and Bernard Courtois (CMP)

  • Dr. May Wu (Director of Wireless System Arch, Intel Labs)

2C – IP Session: How is Industry Simplifying Analog Test?

Room: Pompeian III
Time: 13:40 – 14:40
Organizer: Rubin Parekhji (Texas Instruments)
Moderator: Srinivas Modekurty (Intel Corporation)

  • Analog / Mixed Signal Block Level Structural Test
    Ramana Tadepalli (Texas Instruments)
  • Test Hardware to Support JESD 204C Converter Test
    Jeff Kennedy (Analog Devices)
  • An Integrated Approach to Testing Analog Sub-systems in Large Digital SoC
    Thecla Chomicz (NXP Semiconductors)

3A – Design for test, debug and reliability

Room: Pompeian I
Time: 15:00 – 16:00
Moderator:  Chennian Di (Xilinx)

  • [Best Paper Nominee] Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators
    Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chao (National Chiao Tung University)
  • Flip-flop Clustering based Trace Signal Selection for Post-Silicon Debug
    Yun Cheng (The Institute of Computing Technology of the Chinese Academy of Sciences), Huawei Li (Chinese Academy of Sciences), Ying Wang (The Institute of Computing Technology of the Chinese Academy of Sciences), Xiaowei Li (Institute of Computing Technology, CAS), Gao Yingke, Bo Liu (Beijing Institute of Control Engineering)
  • HLDTL: High-performance, low-cost, and double node upset tolerant latch design
    Aibin Yan (Anhui University), Zhengfeng Huang, Maoxiang Yi, Jie Cui, Huaguo Liang (Heifei University of Technology)

3B – Hot Topic: Intelligent Physical Systems: Test, Diagnosis, Reconfiguration and Correction

Room: Pompeian II
Time: 15:00 – 16:00
Organizer: Abhijit Chatterjee (Georgia Institute of Technology)

  • Context-Aware Self-Optimizing IoT Sensor Nodes
    Shreyas Sen (Purdue University)
  • Error Detection and Learning-assisted Correction in Real-time Systems Using Algorithmic Encoding
    Abhijit Chatterjee (Georgia Institute of Technology)
  • Approximate Computing: Beyond the Tyranny of Digital Abstractions
    Hadi Ismaelzadeh (Georgia Institute of Technology)

3C – IP Session: Hardware Security

Room: Pompeian III
Time: 15:00 – 16:00
Organizer & Moderator: Jeyavijayan Rajendran (UT-Dallas)

  • Robust Secure Design by Increasing the Resilience of Attack Protection Blocks
    Sohrab Aftabjahani (Intel Corporation)
  • System-on-Chip Security for the Internet of Things: Challenges and Recent Trends
    Sandip Ray (NXP Semiconductors)
  • Establishing a trust chain in electronic manufacturing
    Michael Chen (Mentor)

4A – IP Session: Variation-tolerant design of circuits/systems

Room: Pompeian I
Time: 16:20 – 17:20
Organizer & Moderator: Arijit Raychowdhury (Georgia Institute of Technology)

  • Adaptive and resilient high performance memory design for dynamic variation tolerance
    Jaydeep Kulkarni (Intel Corporation)
  • Auto-Calibrating Adaptive Design for Improving Performance and Energy Efficiency while Eliminating Tester Calibration
    Keith Bowman (Qualcomm)
  • Use of Process monitors in Post silicon validation to reduce TTM (time to market)
    Hemanth Shivalingaiah (Intel Corporation)

4B – Hot Topic: Early Life Failures

Room: Pompeian II
Time: 16:20 – 17:20
Organizer: Sybille Hellebrand (University of Paderborn)
Moderator: Hans-Joachim Wunderlich (University of Stuttgart)

  • Brief introduction to Early Life Failures
    Hans-Joachim Wunderlich (University of Stuttgart)
  • Testing and Fault Localization for Embedded Controllers
    Jyotirmoy Deshmukh (Toyota Technical Center)
  • A HW/SW Cross-Layer Approach for Determining Application-Critical Hardware Faults in Embedded Systems
    Wolfgang Kunz (TU Kaiserlautern)

4C – IP Session: Data Analytics in Test

Room: Pompeian III
Time: 16:20 – 17:20
Organizer: Suriya Natarajan (Intel Corporation)
Moderator: Abhijit Sathaye (Intel Corporation)

  • Big Data Analytics Engines for End-to-End Supply Chain and Quality Control
    Thomas Harper, Paul Simon (Qualtera)
  • Data Mining of Defective Parts Investigation in Test
    Rahima Mohammed (Intel Corporation)
  • Intelligent Data Driven Test Eco-system
    Amit Nahar (Texas Instruments)

Monday Evening “Wine and Cheese” Special Session: Test Trivia Game

Room: Pompeian I/II
Time: 20:00 – 21:30
Organizers: Rohit Kapur and Anshuman Chandra (Synopsys), and Gaurav Reddy (UT Dallas)

April, 11th

Registration & Breakfast

Time: 07:30 – 08:30

5A – Memory Test and Repair

Room: Pompeian I
Time: 08:30 – 09:30
Moderator: Ramesh Tekumulla (Broadcom)

  • A Methodology for Estimating Memory Lifetime Using a System-Level Accelerated Life Test and Error-Correcting Codes
    Dae-Hyun Kim, Linda Milor (Georgia Institute of Technology)
  • At-Speed Capture Global Noise Reduction & Low-Power Memory Test Architecture
    Bonita Bhaskaran (NVIDIA Corp.), Sailendra Chadalavada, Shantanu Sarangi (Nvidia), Nithin Valentine (NVIDIA Corp.), Venkat Abilash Reddy Nerallapally (NVIDIA Corp.), Ayub Abdollahian (Nvidia)
  • Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM Cache
    Nour Sayed (KIT – Karlsruhe Institute of Technology), Fabian Oboril, Rajendra Bishnoi (KIT), Mehdi Tahoori (Karlsruhe Institute of Technology)

5B – Reliability Analysis and Yield Optimization

Room: Pompeian II
Time: 08:30 – 09:30
Moderator: Ujjwal Guin (Auburn University)

  • An Analytical Model for Predicting the Residual Life of an IC and Design of Residual-Life Meter
    Md Nazmul Islam, Sandip Kundu (University of Massachusetts Amherst)
  • Learning the Process for Correlation Analysis
    Sebastian Siatkowski (University of California, Santa Barbara), Li-C. Wang (UC Santa Barbara), Nik Sumikawa, LeRoy Winemberg (NXP Semiconductors)
  • Performance-Aware Reliability Assessment of Heterogeneous Chips
    Athanasios Chatzidimitriou, Manolis Kaliorakis, Sotiris Tselonis, Dimitris Gizopoulos (University of Athens)

5C – IP Session: Automotive Test Solutions

Room: Pompeian III
Time: 08:30 – 09:30
Organizer: Peter Sarson (ams AG)
Moderator: Wim Dobbelaere (ON Semiconductor)

  • Automotive IC Testing with BOST Approach
    Ryoji Shiota (Socionext), Haruo Kobayashi (Gunma University)
  • Automotive Alternative Test
    Peter Sarson (ams AG), Constantinos Xanthopoulos (UTDallas)
  • Test methodologies to minimize test cost for Automotive / Safety devices
    Santosh Kavalur (Texas Instruments)

6A – ATPG (II)

Room: Pompeian I
Time: 09:50 – 10:50
Moderator: Vivek Chickermane (Cadence)

  • A Framework for Fast Test Generation at the RTL
    Kelson Gent, Akash Agrawal (Virginia Polytechnic Institute and State University), Michael Hsiao (Virginia Tech)
  • Efficient SAT-Based Generation of Hazard-Activated TSOF Tests
    Jan Burchard, Dominik Erb (University of Freiburg), Sudhakar Reddy (University of Iowa), Adit Singh (Auburn University), Bernd Becker (University of Freiburg)
  • Using Piecewise-Functional Broadside Tests for Functional Broadside Test Compaction
    Irith Pomeranz (Purdue University)

6B – Hot Topic: Physical Attacks: Can Test Save Us?

Room: Pompeian II
Time: 09:50 – 10:50
Organizers: Swarup Bhunia, Mark Tehranipoor (University of Florida)
Moderator: Swarup Bhunia (University of Florida)

  • New Realm in Physical Attacks
    Peter R Munguia (Intel Corporation)
  • Simulation-Based Verification of EM Side-Channel Attack Resilience
    Michael Orshansky (University of Texas at Austin)
  • Attacks on FPGA Bitstream: Piracy & Tampering in Field
    Yousef Iskander (Cisco)

6C – IP Session: DFT for Functional Safety

Room: Pompeian III
Time: 09:50 – 10:50
Organizer: Prashant Goteti (Intel Corporation)
Moderator: Sreejit Chakravarty (Intel Corporation)

  • Autonomous Driving and IOT: Combining Functional Safety, Reliability, Availability and Security for a resilient connected world
    Riccardo Mariani (Intel Corporation)
  • New paradigms for Functional Safety in advances CMOS nodes
    Vincent Huard (ST Micro)
  • Low Overhead Design and Test Techniques for Application Specific Functional Safety
    V. Prasanth, Rubin Parekhji (Texas Instruments)

7A – Hardware Security

Room: Pompeian I
Time: 11:10 – 12:10
Moderator: Swarup Bhunia (University of Florida)

  • A Novel Design-for-Security (DFS) Architecture to Prevent Unauthorized IC Overproduction
    Ujjwal Guin, Zhou Ziqi, Adit Singh (Auburn University)
  • Dynamically Obfuscated Scan for Protecting IPs Against Scan-Based Attacks Throughout Supply Chain
    Dongrong Zhang, Xiaoxiao Wang (Beihang University), Miao HE, Mark Tehranipoor (University of Florida)
  • FISCAL: Firmware Identification Using Side-Channel Power Analysis
    Deepak Krishnankutty (UMBC), Ryan Robucci, Nilanjan Banerjee (University of Maryland Baltimore County), Chintan Patel (UMBC)

7B – Embedded Tutorial: MEMS Testing Challenges, Issues and Solutions

Room: Pompeian II
Time: 11:10 – 12:10
Presenter: Ray Sessego, Tehmoor Dar (Ph.D), Peter Jones (Ph.D) (NXP Semiconductors)

7C – IP Session: Automotive Quality Assurance

Room: Pompeian III
Time: 11:10 – 12:10
Organizer & Moderator: Peter Sarson (ams AG)

  • Adapting IEEE 1687 PDL for Writing Analog Tests
    Jeff Rearick (AMD)
  • Testing of mixed signal automotive circuits: do we guarantee the spec or do we catch defects?
    Wim Dobbelaere (ONSemi)
  • Meeting quality for Automotive Application with IO interfaces
    Salem Abdennadher (Intel Corporation)

8A – Hot Topic: Future Extensions of IEEE Test Standards

Room: Pompeian I
Time: 13:30 – 14:30
Organizer: Jennifer Dworak (Southern Methodist University)
Moderator: Yu Huang (Mentor Graphics)

  • From 1687 to 1687.1
    Martin Keim (Mentor Graphics)
  • Extending IEEE 1687 for Use on Analog / Mixed-Signal Chips
    Jeff Rearick (AMD)
  • IEEE Std P1838: DFT Up and Down the Stack
    Adam Cron (Synopsys)

8B – New Topic: Designing Versatile Semiconductor Solutions Optimizing Performance, Power, & Cost to Market Opportunities

Room: Pompeian II
Time: 13:30 – 14:30
Organizer: Bozena Kaminska (Simon Fraser University) and Bernard Courtois (CMP)

  • Chafik Behidj (Global Foundries)

8C – Special Session: E.J. McCluskey Doctoral Thesis Competition (Presentations & Posters)

Room: Pompeian III
Time: 13:30 – 15:00
Organizers: Michele Portolan (TIMA Laboratory), Naghmeh Karimi (University of Maryland Baltimore County)
Moderator: Naghmeh Karimi (University of Maryland Baltimore County)

VTS 2017 Semifinalists:

  1. Robert Karam (University of Florida), Advisor: Swarup Bhunia
    Thesis title: Energy-Efficient and Secure Reconfigurable Computing Architecture
  2. Yu Liu (The U. of Texas at Dallas), Advisor: Yiorgos Makris
    Thesis title: Hardware Trojans in Wireless Cryptographic ICs
  3. Cheng Xue (Carnegie Mellon University), Advisor: R.D. (Shawn) Blanton
    Thesis title: Optimizing IC Testing for Diagnosability, Effectiveness and Efficiency
  4. Yuming Zhuang (Iowa State University), Advisor: Degang Chen
    Thesis title: Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements

Social Event

Time: 15:30 – 21:30

April, 12th

Registration & Breakfast

Time: 07:30 – 08:30

9A – Analog, Mixed-Signal and RF Test (II)

Room: Pompeian I
Time: 08:30 – 09:30
Moderator: Haralampos Stratigopoulos (UMPC-LIP6)

  • A low-cost method for separation and accurate estimation of ADC noise, aperture jitter, and clock jitter
    Shravan Chaganti (Iowa State University), Li Xu (Texas Instruments), Degang Chen (Iowa State University)
  • Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs
    Guillaume Renaud, Marc Margalef-Rovira, Manuel Barragan, Salvador Mir (TIMA Laboratory)
  • Knob Non-Idealities in Learning-Based Post-Production Tuning of Analog/RF ICs: Impact & Remedies
    Yichuan Lu, Georgios Volanis, Kiruba Subramani, Angelos Antonopoulos, Yiorgos Makris (UT Dallas)

9B – IP Session: Innovative Practices in Asia (I): From Quality Perspective

Room: Pompeian II
Time: 08:30 – 09:30
Organizers: Kazumi Hatayama (Gunma University),
Masahiro Ishida (Advantest)
Moderator: Masahiro Ishida (Advantest)

  • Utilizing Switch-Level Test Generation to Improve Accuracy and Efficiency of Cell-Aware Fault Modeling
    Harry H. Chen (Presenter), Simon Y-H. Chen (MediaTek Inc.), Po-Yao Chuang, Cheng-Wen Wu (National Tsing Hua University)
  • Soft-Error Rate Evaluation Utilizing Low-Energy Neutron Beam
    Takumi Uezono (Presenter), Tadanobu Toba, Kenichi Shimbo, Fumihiko Nagasaki, and Kenji Kawamura (Hitachi)
  • Power-on and Electrical Validation of High Speed IO using direct IP bring-up on partially-functional SOC ICs
    Nitin Chaudhary (Intel Corporation)

9C – IP Session: DFT and Data for Diagnostics

Room: Pompeian III
Time: 08:30 – 09:30
Organizer: Kun Young Chung (Qualcomm)
Moderator: Stefano Di Carlo (Politecnico di Torino)

  • Using Cell Aware Diagnosis to Speed up Yield Ramp for FinFET Technology
    Huaxing Tang (Mentor Graphics)
  • Integrated Yield Learning with Logic and Memory Volume Diagnostics
    John Kim (Synopsys)
  • DFM-aware fault model
    Arani Sinha (Intel Corporation)

10A – Test Economics and Test Standards

Room: Pompeian I
Time: 09:50 – 10:50
Moderator: Jennifer Dworak (Southern Methodist University)

  • Structured Scan Patterns Retargeting for Dynamic Instruments Access
    Ahmed Ibrahim, Hans Kerkhoff (University of Twente)
  • Test-Cost Optimization in a Scan-Compression Architecture Using Support-Vector Regression
    Zipeng Li (Duke University), Jon Colburn (NVIDIA), Vinod Pagalone (NVIDIA Corporation), Kaushik Narayanun (NVIDIA Corp.), Krishnendu Chakrabarty (Duke University)

10B – IP Session: Innovative Practices in Asia (II): From Cost Perspective

Room: Pompeian II
Time: 09:50 – 10:50
Organizers: Kazumi Hatayama (Gunma University), Masahiro Ishida (Advantest)
Moderator: Kazumi Hatayama (Gunma University)

  • Optical Interconnection Test Method
    Kazuki Shirahata, Tasuku Fujibe, Masahiro Ishida, Daisuke Watanabe, Tomoyuki Itakura, Hidenobu Matsumura, Hiroyuki Mineo, Shin Masuda, Dave Armstrong (Advantest America Inc.)
  • Signal Generation with Specified Harmonics Suppression Using Only Single Digital Output Pin
    Masayuki Kawabata, Koji Asami (Advantest Corporation), Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi (Gunma University)
  • A Practical and Cost Effective Approach for 2.5D FPGA-Transceiver EMIB Testing
    Lai Pheng Tan, Shen Shen Lee, and Kian Hui Wong (Intel Corporation)

10C – IP Session: Formal verification practices in industry

Room: Pompeian III
Time: 09:50 – 10:50
Organizer: Huawei Li & Xiaowei Li (ICT, CAS)
Moderator: Huawei Li (ICT, CAS)

  • Formal Verification Techniques and Trends in Industry
    Jun Yuan (Arcas Tech)
  • Finding Deep RTL Bugs Through Formal Verification
    Xiushan Feng (Samsung)
  • Formal Verification Applied in GPU Designs
    Rachel Fan (AMD)

11A – Test Quality and Reliability

Room: Pompeian I
Time: 11:10 – 12:10
Moderator: Hans Manhaeve (Ridgetop)

  • Asymmetric sizing: an effective design approach for SRAM cells against BTI aging
    Xuan Zuo, Sandeep Gupta (University of Southern California)
  • Comprehensive Investigation of Gate Oxide Short in FinFETs
    Roya Dibaj (Carleton University), Dhamin Al-Khalili (Dept. of Elec. & Comp. Eng. Royal Military College), Maitham Shams (Dept. of Electronics, Carleton University)
  • On-Line Diagnosis and Compensation for Parametric Failures in Linear State Variable Circuits and Systems Using Time-Domain Checksum Observers
    Md Momtaz, Suvadeep Banerjee, Abhijit Chatterjee (Georgia Institute of Technology)

11B – Panel: Would you put your life in the hands of a Google Car?

Room: Pompeian II
Time: 11:10 – 12:10
Organizer/Moderator: LeRoy Winemberg (NXP Semiconductors)

11C – IP Session: SOC Testing

Room: Pompeian III
Time: 11:10 – 12:10
Organizer: Yu Huang (Mentor Graphics)

  • High Bandwidth DFT Fabric for SoCs
    Jon Easter (Intel Corporation)
  • Modular Test Practices in High-End FPGA
    Chunsheng Liu (Intel Corporation)
  • A SoC Test Methodology for DFT Engineering Performance Improvements
    Martin Keim (Mentor Graphics)

12A – Hot Topic: 5G Test Challenges: A System-level Perspective

Room: Pompeian I
Time: 13:30 – 14:30
Presenter: Adam Smith (LitePoint)

12B – Embedded Tutorial (I) – Emerging Non-volatile memories: Trends, Technologies and Test Topics

Room: Pompeian II
Time: 13:30 – 14:30
Organizer & Moderator: Mehdi Tahoori (Karlsruhe Institute of Technology)

  • Security and resiliency of non-volatile memories: How test can help?
    Swaroop Ghosh (Penn State University)
  • Spintoronics Memories: Past, Present and Future
    Tomishima Shigeki (Intel Labs)

12C – Embedded Tutorial (II): Software Testing: Challenges and Emerging Solutions

Room: Pompeian III
Time: 13:30 – 14:30
Organizer: Dr. Indradeep Ghosh (Fujistu Labs)
Moderator: Stefano Di Carlo (Politecnico di Torino)

  • Software test challenges: techniques and emerging trends
    Indradeep Ghosh (Fujistu Labs)
  • Embedded Software Testing: Challenges and Approaches
    Yashwant Malaiya (Colorado State University)