High Bandwidth DFT Fabric for SoCs

Speaker: Jon Easter (Intel Corporation)

Abstract: Today’s SoCs contain large numbers of partitions with varying geometries which pose significant challenges for DFT fabrics. These SoCs require fabric solutions to enable efficient, low-cost, and high quality manufacturing test. The fabric must also have support for different types of DFT content and allow for DFT content reuse. This presentation will discuss the features of the high bandwidth DFT fabric, discuss its construction, and provide an overview of how this DFT fabric solution is used in SoCs.

Modular Test Practices in High-End FPGA

Speaker: Chunsheng Liu (Intel Corporation)

Abstract: The requirements in test cost and quality for high-end FPGA are becoming prohibitively demanding. Current FPGA incorporates standard logic blocks, memory blocks, DSPs, standardized sub chips and various IPs for processing, inter-block and inter-chip links. Testing such a hybrid system with high coverage and low test time requires different solutions to cover different modules. In this talk, we will discuss some existing challenges in testing an FPGA system and several practices that are being employed. We will discuss both standard and in-house practices in testing FPGA fabric modules and IP modules, and future directions on how to integrate various modular tests into a low cost test plan.

A SoC Test Methodology for DFT Engineering Performance

Speaker: Martin Keim (Mentor Graphics Corporation)

Abstract: IEEE 1687 (IJTAG) sets out to become the defacto methodology for incorporating IP (instruments) of various sources. Some of these instruments we know very well from the performed DFT tasks in about every design there is, memory and logic BIST, boundary scan, but also embedded compression ATPG. In this presentation we look at how IJTAG increases your effectiveness for the tasks of DFT planning, insertion, and subsequent true hierarchical pattern generation for the various DFT instruments you use every day.

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