Using Cell Aware Diagnosis to Speed up Yield Ramp for FinFET Technology

Speaker: Huaxing Tang (Mentor Graphics)

Abstract: Diagnosis driven yield analysis (DDYA) based on layout aware diagnosis results for volume failure data has been widely adopted for yield learning. Layout aware diagnosis analyzes failure test data and calls out suspects of interconnect bridges and interconnect opens, and cells at cell boundary. Recently the semiconductor industry is seeing an increasing number of cell internal defects for FinFET technology, due to extremely small feature size, complex cell design and sophisticated manufacturing process.  Cell aware diagnosis (CAD) has been proposed to pinpoint the defect location within a defective cell by using accurate defect models derived from analog simulation. Based on CAD results with accurate cell internal defect information, DDYA flow can handle cell related yield limiters better and thus speed up the yield ramp for FinFET technology.

Integrated Yield Learning with Logic and Memory Volume Diagnostics

Speaker: John Kim (Synopsys)

Abstract: With the advancements in process technology, increased process-design interactions and shortened production lifecycles, it is important to quickly ramp up a new design from insertion yields to stable production defect densities. Traditional product engineering methods by themselves become stretched to identify root cause of failures and identify owners that can quickly spin a fix (whether that be a process fix or a design fix). Adding details from both logic and memory diagnostics into the yield learning process can provides an additional angle of analysis to help come to conclusions and allow product teams to move on to the next problem, or product. We will discuss various practices where having both logic and memory diagnostics can greatly improve the product/yield engineer’s time to conclusion.

DFM-aware fault model

Speaker: Arani Sinha (Intel Corporation)

Abstract: Yield improvement, yield ramp and defect screening have been major areas of concern for the semiconductor industry as technology nodes have advanced. Besides stuck-at and transition testing, critical area has traditionally been used as the manufacturability guideline to determine opens and shorts that should be targeted for test. This talk will motivate a new paradigm – a design-for-manufacturability (DFM) hotspot-aware fault model to target intra-cell and inter-cell defects. The basic objective behind this approach is to use knowledge of manufacturing vulnerability in design layouts to weigh likelihood of occurrence of systematic defects. Targeted pattern generation for DFM faults can lead to accelerated identification of systematic defects during yield ramp, and reduce pattern count in high volume manufacturing. Diagnosis feedback from silicon during HVM test can re-prioritize DFM guidelines as well as introduce new guidelines, leading to yield improvement.

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