Fast yield learning method using correlation of manufacturing defects on circuits based on DFM rule check

Speaker: Tapan Chakraborty (Qualcomm)

Abstract: In this work, we present a fast yield learning method using correlation of defects on a circuit to the design for manufacturing (DFM) rules violated areas on the layout of a circuit. These circuit nodes are more vulnerable to defects as they violate the DFM rules which are recommended for a manufacturing process.
This method consists of two steps. In the first step, we run DFM rule checks on the final layout (final tape-out database) of a chip and violations are identified in terms of coordinates of the violating structures on the layout.
Then DFM rule violated areas are correlated with normal volume diagnostics data developed based on scan based structural tests used as manufacturing test. As a result defective circuit nets & instances are identified which correlates with DFM rule violated areas and corresponding yield loss is computed. This yield loss is due to the DFM rule violations on the circuit, which are not mandatory fix category to begin with. Therefore, these corresponding DFM rules are considered to be must fix category for subsequent designs going forward which uses the same process node for fabrication. This way a multiple number of defects can be cured simultaneously and no PFAs are necessary which is very time consuming & sequential process.
This method results in faster yield learning & improvements compared to the traditional method of yield learning using PFA of each defects identified on silicon.

Screening Yield Systematics Through Holistic Volume Diagnosis in a Leading-edge Foundry

Speaker: Yan Pan (Global Foundries)

Abstract: With the shortening lifetime of semiconductor ICs in the market, delays in early yield ramps and subsequent high volume production can derail new product introductions. This can compromise the profitability of both fabless and foundry companies. With the increasing complexity of both the product designs and the foundry technologies, the complex interplay of design and technology is stressing the fabless-foundry model, where yield was traditionally viewed as the foundry’s responsibility. To identify design & layout-specific failure modes as quickly as possible, a foundry needs to drive the learning through multiple domains, from early technology test chip planning, DFT recommendations to fabless customers, to building a sophisticated data analysis framework that leverages multiple data sources for volume-based analysis. Through case studies and examples from GLOBALFOUNDRIES, we will explain both best practices in volume-based diagnosis analysis, as well as how to leverage design characteristics such as layout analysis for fast screening of layout-systematic defects.

Physical pattern analysis to identify test escape risks

Speaker: Ya-Chieh Lai (Cadence Design Systems)

Abstract: Recent advances in layout analysis have allowed efficient decomposition of large full chip designs, enabling the cataloging of the entire physical design space of layout into constituent physical patterns.   Note that the term physical patterns used here refers to layout patterns and not test patterns.  By building an index of all possible layout constructs (including coverage of both single layer and multi-layer constructs) and correlating this physical pattern space with the space of known tested logical nets, it is possible not only to identify the physical locations of a design that are not tested, but also to identify physical patterns that do not belong to the set of physical patterns in the tested areas of a design and are therefore fully uncovered and untested.
Further, many foundries have been building their own databases of known physical weak points.  With the same analysis, we can find the coordinates in a design that match those physical weak point patterns.  Given the coordinates and layers in the layout corresponding to those physical weak points (and if available, the nature of the expected defect), appropriate faults can be generated and actively targeted for ATPG, or simply checked to see if they are covered by existing tests.
We will share the results of this type of analysis used to compare the physical design space of tested vs untested nets and to demonstrate how this can be applied to better understand the physical design space coverage as testability is increased. We will also show how this type of analysis can be applied to screen for physical weak points.

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