Utilizing Switch-Level Test Generation to Improve Accuracy and Efficiency of Cell-Aware Fault Modeling

Speaker: Harry H. Chen (MediaTek Inc.)

Abstract: Current cell-aware fault modeling methods suffer from two serious limitations. Stand-alone cell characterization loses accuracy when defect behavior depends on design context. Over-reliance on analog fault simulation is wasteful and expensive. Adopting switch-level test generation can enable in-situ defect characterization to improve accuracy and eliminate unnecessary analog fault simulation for many types of defects. Experimental results show characterization speed-up by at least two orders of magnitude.

Soft-Error Rate Evaluation Utilizing Low-Energy Neutron Beam

Speaker: Takumi Uezono (Hitachi)

Abstract: The measurement of soft-error tolerance of devices is one of key technologies to guarantee quality reliability. In this presentation, we propose a method to measure soft-error rate in terrestrial environment irradiating with a low-energy neutron beam. Our proposed method can reduce the measurement cost comparing the conventional methods utilizing high-energy neutron beam. We applied our proposed method to FPGAs fabricated in 90nm, 65nm, 40nm, and 28nm processes, and compared the results with those of conventional methods. The comparison results shows the accuracy of our proposed method is comparable with that of conventional ones for the CRAMs of FPGAs fabricated in processes less than 40 nm.

Power-on and Electrical Validation of High Speed IO using direct IP bring-up on partially-functional SOC ICs

Speaker: Nitin Chaudhary (Intel Corporation)

Abstract: The ‘partially-functional’ SOC ICs are silicon chips unusable from system perspective and have manufacturing or other issues impeding full-chip reset and boot flow. These are common in any product or IPs’ power-on on a new process technology. In case of a new product with no prior usable boards, the newly designed boards may also have defects. The various reworks and fixes implemented on these boards makes them unstable for high speed IO characterization or adds to the debug complexity. As we know, SOC business depends heavily on time to market and product power-on and electrical validation execution is in the critical path so a shortage of working silicon chips and a limitation of moving them across boards makes power-on even more challenging. Intel’s High Speed Serial I/O IPs use test methods that enables power-on and quick electrical validation checks in just few hours of getting first ‘partially-functional’ silicon. This facilitates a timely PHY characterization and a quick enabling of High Volume Manufacturing. This presentation describes test strategies, tools and use of emulation that helped in a successful and quick power-on and electrical validation closure. These methods are used in characterization during silicon bring-up or post-silicon validation.

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