Analog / Mixed Signal Block Level Structural Test

Speaker: Ramana Tadepalli (Texas Instruments)

Abstract: With continued growth of the Automotive & Industrial semiconductors market, large analog SOC products need test screens that guarantee 0 DPPM quality and thus test is becoming more challenging and is an increasingly significant cost adder. This presentation discusses methods of structural test planning and test suite implementation for such devices, focusing on ensuring coverage and validating performance of silicon, while maintaining low test cost with minimum DFT overhead. The effectiveness of the method both in terms of quality improvement and throughput increase is also shown via a case study on two near identical devices with different test design methods in volume production testing.

Test Hardware to Support JESD 204C Converter Test

Speaker: Jeff Kennedy (Analog Devices)

Abstract: As usual the bleeding edge of high speed converters stay ahead of the ATE ability to test them. It is not just the traditional ATE short-comings like fidelity of input stimulus, bandwidth output measure and low noise clocking, but it is the data transfer rates that also need to be addressed. The JESD interface was introduced around 2008 to move high speed converters away from traditional CMOS and LVDS I/O to serial interfaces that brought advantages in speed, size and cost. The first JESD revision 204a had max data rates of 3.125Gbps, the next 204b topped out at 12.5Gbps and soon 204c will be at 32Gbps.This rapid increase in just over 8 years has challenged ATE companies’ ability to keep pace. The challenges of moving and processing serial data at these rates are plentiful. This presentation will talk about those challenges and the test hardware that allows you to overcome them.

An Integrated Approach to Testing Analog Sub-systems in Large Digital SoC

Speaker: Thecla Chomicz (NXP Semiconductors)

Abstract: Testing large analog subsystems within even larger digital SoCs requires an integrated approach from day one. This presentation will identify how to align the overall test strategy to various expectations of “test” across disciplines. These expectations include testing for manufacturing anomalies, validating against industry specifications and the ability to debug issues. Once the various test expectations are defined, the analog sub-system is analyzed to expose critical components needed for test access and in-application observation. Lastly, a method that allows for quick turnaround in test development targeting a number of different environments including simulation, production test and bench top testing, will be discussed.

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