Adaptive and resilient high performance memory design for dynamic variation tolerance

Speaker: Jaydeep Kulkarni (Intel Corporation)

Abstract: Traditional approaches of voltage/frequency guard banding in memory circuits and register files decrease the overall system efficiency. These calls for radical approaches to resiliency and dynamic adaptation to minimize such overheads. This talk will present an adaptive and resilient domino register file design featuring in-situ timing margin and error detection for the performance-critical domino read path. Voltage/frequency is adapted for slow-changing variations such as low-frequency supply noise, temperature fluctuation, and aging-induced degradation. Dynamic adaptation is combined with error detection and recovery for fast voltage droops and random data access patterns in the presence of within-die process variations. Throughput and energy efficiency gains are higher than the replica/canary based critical path approach. Timing margin is tracked by double-sampling the read output and its delayed version at the same clock edge. Timing errors are detected by double-sampling and comparing the read output within a clock window. The sensing errors in the precharge/evaluate domino read path are converted into timing errors using a conditional delayed-bitline precharge technique that does not impact the subsequent precharge operation. The measurement results from a 22nm tri-gate CMOS testchip demonstrate 21% throughput and 67% energy efficiency improvement with a peak energy efficiency of 409 GOPS/W. Having in-situ timing margin detection can accelerate the debug of speedpath or marginal bits, and can enable better understanding of the ideal guardbands to be applied. Thus it can be used purely as a debug/test technique in addition to the full resiliency application.

Auto-Calibrating Adaptive Design for Improving Performance and Energy Efficiency while Eliminating Tester Calibration

Speaker: Keith Bowman (Qualcomm)

Abstract: An auto-calibrating adaptive clock distribution (ACD) recovers the processor performance loss from supply voltage (Vdd) droops while eliminating the expensive tester calibration in traditional adaptive designs. The auto-calibration circuit enables in-field, low-latency tuning of the dynamic variation monitor to accurately detect Vdd droops across a wide range of operating conditions to maximize the ACD benefits. Silicon measurements demonstrate simultaneous throughput gains and energy reductions ranging from 13% and 5% at 0.9 V to 30% and 13% at 0.6 V, respectively, for a 10% Vdd droop.

Use of Process monitors in Post silicon validation to reduce TTM (time to market)

Speaker: Hemanth Shivalingaiah (Intel Corporation)

Abstract: Post silicon validation of the PHY requires that the circuits are validated to account for the variations in manufacturing process. Targeted silicon skews guarantee the design functionality for variations in the transistor parameters that are possible from the fab. However the time taken to obtain targeted skew silicon can be a few weeks after the initial silicon lots are released. This gap in time is too long for a company looking to reduce the TTM of its products. In this talk, I describe how a process monitor circuit built into the PHY can be used to get an initial assessment of silicon performance by “guesstimating” the skew of the silicon. The process monitor cells are incorporated into the design to provide an indication of the silicon skew. These indicators are then used by the various components in the PHY, like the Receiver, Transmitter, PLL and the clock distribution to scale the biases or the timing parameters to compensate for the process variations. In addition to the process monitoring cells there are compensation loops for the resistors with scaling options (RCOMP) and there are options to dial in different values of current/voltage biases. The electrical validation (EV) teams can use these three options (Process monitor cell, RCOMP scalars and bias dialers) to stress the circuits in the PHY to expose marginalities in functionality and performance.

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