Formal Verification Techniques and Trends in Industry

Speaker: Jun Yuan (Arcas Tech)

Abstract: In this talk I will give a brief review of formal verification, its status today, and roadmaps. I first encountered formal verification more than a quarter of a century ago when I took a class called Formal Logics. It was rigid and dry. Unfortunately, even today the very word formal still arouse the same feeling in most people. In fact, formal verification is a school of thoughts that come together from multiple origins: philosophy, logic, mathematics, operational research, and artificial intelligence, to name a few. The beauty and succinctness of mechanical reasoning is the driving force behind all this.
At a point of time, formal verification seemed to have painted itself to the corner of NP-completeness. Unlike optimization problems which benefit from quantitative enhancements, formal verification is a hard decision problem that only takes a qualitative yes or no as the answer. Apart from its computational complexity, it is further black eyed by the underlying formality. Then why is formal verification still alive and kicking and even becoming prosperous today? It’s due to progresses in three areas, technical, applicational, and methodological.
Among the troops of Genghis Khan that drove thousands of miles to the west, there was a special force consisting of hundreds of Chinese technicians. Their only role was to operate a few clumsy big cannons. Why bother? Because fire powered weaponry was a sheer revolution in those days. And look where we are a thousand year later. I’m a firm believer that formal verification, with its unique approach and advantages, will be an even wider spread success in the ever increasingly difficult task of semiconductor design, today and tomorrow

Finding Deep RTL Bugs through Formal Verification

Speaker: Xiushan Feng (Samsung)

Abstract: Formal verification has become a must-have approach in design verification flow for circuit design companies. Based on mathematical reasoning, formal verification can fully prove correctness for a design with limited state space. However, with the increasing complexity of designs, oftentimes, formal verification cannot provide conclusive poofs and may easily struggle with low proof bounds for proof-based engines. For such designs, finding deep RTL bugs has much higher return than fully proving the correctness. Leveraging with search-based semi-formal engines, techniques, such as user-guided formal bug hunting, can be used to explore deep design space where potential bugs may exist. In this talk, the authors will present ideas on how to find RTL bugs that are escaped in simulation using real examples. With formal-specific assertions and state-space abstraction, complicated designs, such as caches, can be explored by formal with high coverage for potential deadlock bugs. Catching such RTL bugs demonstrates the power of formal bug hunting techniques.

Formal Verification Applied in GPU Designs

Speaker: Rachel Fan (AMD)

Abstract: The modern GPU is a highly parallel, highly multithreaded multiprocessor optimized for visual and general-purpose computing. Accompanying with the innovations in the areas of AR, VR and AI, the GPU architecture keeps evolving to maximize the computing performance and throughput. Consequently, the complexity of the GPU implementation keeps increasing in both thread scheduling and data processing. The traditional simulation-based verification methodology is facing big challenges, in either verification workload or coverage. Formal verification, as a systematic process of ensuring that design implementation satisfies the spec, shows advantages in handling with control-intensive logic and certain data-path design. This talk presents how AMD Graphics IP team adopted formal verification, introducing different abstraction techniques for conquering non-trivial control-intensive designs, and how to leverage word-level reasoning and transaction equivalence check for the proof on the critical ALU design. Result data will also be analyzed to show the return-on-investment, in comparison with simulation-based verification.

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