Brief introduction to Early Life Failures

Speaker: Hans-Joachim Wunderlich (University of Stuttgart)

Testing and Fault Localization for Embedded Controllers

Speaker: Jyotirmoy Deshmukh (Toyota Technical Center)

Abstract: The model-based development paradigm is increasingly being used for designing embedded controllers in the cyber-physical systems (CPS) domain. The main motivation is to identify and eliminate possible issues in the system design at an early development stage. This is made possible by having reasonably high-fidelity plant models that capture the physical aspects of the CPS system, and controller models designed using a visual, block-diagram based programming language such as Simulink from the Mathworks. A challenge is that control designers often do not have machine checkable requirements on the overall behavior of the closed-loop model (consisting of the plant and the controller models). We suggest the use of Signal Temporal Logic as a candidate formalism to model such requirements. Furthermore, we consider techniques to automatically generate interesting test cases, and localize faults in the closed-loop model using methods drawn from black-box optimization and statistical analysis.

A HW/SW Cross-Layer Approach for Determining Application-Critical Hardware Faults in Embedded Systems

Speaker: Wolfgang Kunz (TU Kaiserlautern)

Abstract: Hardware devices of recent technology nodes are intrinsically more susceptible to faults than previous devices. Early life failures contribute increasingly to testing costs and jeopardize the safety of the overall system. This calls for new methods of error detection and for a sophisticated on-chip testing infrastructure. However, any attempt to cover all errors for all theoretically possible scenarios that a system might be used in can easily lead to excessive costs. Instead, an application-dependent approach should be taken, i.e., strategies for test and error resilience must target only those errors that can actually have an effect in the situations in which the hardware is being used.
In this talk, we describe a method to inject faults into hardware (HW) and to formally analyze their effects on the software (SW) behavior. We describe how this analysis can be implemented based on a HW-dependent software model called program netlist (PN). We show how program netlists can be extended to formally model the behavior of a program in the event of one or more hardware faults. A PN-based analysis is presented capturing the effects of faults in the architectural states of the system and at the software level. Then, it is shown how these results can be related precisely with gate-level faults located anywhere in the hardware. We present a method that exploits standard gate-level ATPG in combination with constraints obtained from PN-level analysis to determine hardware faults at the gate level that are "application-redundant". Our experimental results show the feasibility of the proposed approach and point out its application in safety analysis for embedded systems.

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