Autonomous Driving and IOT: Combining Functional Safety, Reliability, Availability and Security for a resilient connected world

Speaker: Maria Spence (Intel Corporation)

Abstract: The aim of the presentation is to educate attendees on Functional Safety, describe the relationships with other disciplines such as Test, Reliability and Security. The presentation will include tangible examples (e.g. on autonomous driving) based on the experience of the presenter in specifying and designing fault tolerant systems.

New paradigms for Functional Safety in advances CMOS nodes

Speaker: Vincent Huard (ST Micro)

Abstract: Recently, driven by autonomous driving needs, automotive products have been pushed forward to advanced CMOS nodes, which are more subjected to process variability and reliability drifts.
In parallel, the normative aspects had become more stringent with the application of ISO26262 norm. This norm does not describe in details which methods and techniques to be applied in fulfilling the stated requirements, which triggers a lots of research activities.
In this paper, various methods and techniques ranging from hazard and risk assessment through a cross-layer approach to the development of system countermeasures and dynamic adaptation will be presented to assist the automotive products for implementing this new standard.

Low Overhead Design and Test Techniques for Application Specific Functional Safety

Speakers: V. Prasanth, Rubin Parekhji (Texas Instruments)

Abstract: As integrated circuits find increasingly pervasive use in safety critical applications, achieving chip level compliance to safety standards to enable applications which are also compliant, is progressively becoming a norm. At the chip level, this involves meeting the specified Single Point Fault Metric (SPFM) and Latent Fault Metric (LFM) for both permanent and transient faults within the specified Fault Tolerant Time Interval (FTTI) and latent fault check interval respectively. Techniques used to meet the functional safety goals can be grouped into hardware, firmware or application based. These offer different tradeoffs in design / execution overhead, error detection / tolerance, and latency in taking corrective action. In this presentation, we discuss various options using a closed loop control application as an example. More specifically, we will cover different safety mechanisms enabled through hardware BIST (including handling of real-time interrupts), software execution check using signatures, background memory self-test, and smart adoption of other check / diagnostics mechanisms, to meet various functional safety goals. We also review how these test mechanisms themselves are handled for overall device safety.

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