From 1687 to 1687.1

Speaker: Martin Keim (Mentor Graphics)

Abstract: IEEE 1687-2014 (IJTAG) is seeing wide spread adoption for a large variety of designs. However, there is one particular type of designs, that cannot (easily) use IJTAG. Common to these designs is that they do not have a top level, IEEE 1149.1-compliant TAP controller, but use other interfaces, like SPI, I2C, or similar in-house interfaces. IEEE P1687.1 addresses this problem. In this talk, we summarize the current thinking of the working group to create a general methodology for connecting such interfaces at the chip IO to an internal IJTAG network.

Extending IEEE 1687 for Use on Analog / Mixed-Signal Chips

Speaker: Jeff Rearick (AMD)

Abstract: Analog DFT has been a largely ad hoc process for, well, forever. Now that IEEE 1687 has standardized the methods for writing portable patterns and describing access mechanisms for digital circuits, there is real progress being made in extending these approaches to include analog and mixed-signal circuits. This talk will explain how two analog DFT hardware solutions (analog test bus and streaming ADC/DAC access) can be represented in 1687 ICL and PDL.

IEEE Std P1838: DFT Up and Down the Stack

Speaker: Adam Cron (Synopsys)

Abstract: Abstract: Stacked digital die are slow in coming, but true believers are optimistic that this technology is inevitable as the world tries to pack more and more functionality into smaller and smaller spaces. A key enabler to 3D die stacking is Test. DFT for stacked die scenarios is being developed by the IEEE Std P1838 Working Group. This session will explain the serial and broadband access mechanisms for such a stack of die.

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