Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Prior to joining Stanford, he was a Principal Engineer at Intel Corporation.

Prof. Mitra’s research interests include robust system design, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications. His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer, and it was featured on the cover of NATURE. The National Science Foundation (NSF) presented this work as a Research Highlight to the United States Congress, and it also was highlighted as “an important, scientific breakthrough” by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.

Prof. Mitra’s honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, a “test of time” honor for an outstanding technical contribution, and the Intel Achievement Award, Intel’s highest corporate honor. He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors “for being important to them during their time at Stanford.”

Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on the Defense Advanced Research Projects Agency’s (DARPA) Information Science and Technology (ISAT) Board as an invited member. He is a Fellow of the ACM and the IEEE.

Yiorgos Makris (U Texas at Dallas) is a professor in the department of Electrical Engineering at the Erik Jonsson School of Engineering & Computer Science at The University of Texas at Dallas, since July 2011. Prior to joining UT Dallas, he spent 10,5 yeas as a faculty of Electrical Engineering and of Computer Science at Yale University. He holds a Ph.D. (2001) and an M.S. (1997) in Computer Engineering from the University of California, San Diego, and a Diploma of Engineering (1995) in Computer Engineering and Informatics from the University of Patras, Greece. He is the 2016 general chair and was the 2013-2014 program chair of the IEEE VLSI Test Symposium as well as the 2010-2012 program chair of the Test Technology Educational Program (TTEP). He is as an associate editor of the IEEE Design & Test periodical and the Springer Journal of Electronic Testing: Theory and Applications and has also served as a guest editor for the IEEE Transactions on Computers and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and as a topic coordinator and/or program committee member for several IEEE and ACM conferences. He is a Senior Member of the IEEE, a recipient of the 2006 Sheffield Distinguished Teaching Award and a recipient of the Best Paper Award from the 2013 Design Automation and Test in Europe (DATE’13) conference.

Robert C. Aitken (ARM, USA) is an ARM Fellow and technology lead for ARM Research. His areas of responsibility include technology roadmapping, library architecture for advanced process nodes, and low power design. His research interests include design for variability, resilient computing, and memory robustness. His group has participated in numerous chip tape-outs, including 8 at or below the 16nm node. He has published over 70 technical papers, on a wide range of topics. Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He has given tutorials and short courses on several subjects at conferences and universities worldwide. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees. 

Paul G Ryan (Intel, USA) received his Ph.D. in Electrical and Computer Engineering from the University of Illinois at Champaign-Urbana in 1994.  He is now a Sr. Principal Engineer in the Technology and Manufacturing Group at the Intel Corporation.  His work focuses on building predictive models of manufacturing defects and outgoing test quality to drive upstream solutions that range across architecture / design for test, fault models / test generation, and manufacturing test methods.

Jonathan Chang (TSMC) is a director leading Memory Solution Division at TSMC. He is responsible for delivering embedded memory IP’s including SRAM compilers, custom SRAM IPs, efuse IPs for low power, high speed applications for advance technology nodes. Before joining TSMC in 2010, Jonathan had been with Intel Corporation, Santa Clara, CA since 1998 and had been engaged in the design of several high-performance microprocessors with emphasis in large, high-speed, low power cache design.  He was a Principal Engineer in the area of cache design in Enterprise Microprocessor Group.

Jonathan is a senior member of the IEEE since 2006 and serves as a technical program committee member of Memory subcommittee for 2013/2014/2015/2016 ISSCC. Jonathan serves as technical program committee member of VLSI symposium on circuits in 2016 (JFE) and 2011 (NAE) and technical program committee member of International Test Conference in 2014. Since 2011, Jonathan has been the associate editor of IEEE Trans on VLSI.  Jonathan has published 20+ technical papers in IEEE conferences or journals and held 5 patents with additional 15 pending in SRAM design.

Jonathan Chang received the B.S. degree in electrical engineering from National Taiwan University, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA.

Dr. Yervant Zorian (Synopsys) is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia’s National Medal of Science.

He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Jacob Abraham (U Texas at Austin, USA)  has been active in the area of test for forty years.  He received his Ph.D. in Electrical Engineering and Computer Science from Stanford University in 1974.  He was a faculty member at the University of Illinois in Urbana-Champaign from 1975 to 1988, where he developed the first high-level, “functional” fault models for memories and microprocessors, and showed that “coupling” faults between any pair of memory cells could be detected by an O(n) algorithm.  He also invented the “algorithm-based fault tolerance” technique which uses information about the computation being performed to detect and correct errors due to faults.

Prof. Abraham has been at the University of Texas at Austin since 1988, where he holds an endowed chair in Engineering.  At Texas, he devised a fault injection system, emulating hardware faults using software, to evaluate fault-tolerance capabilities of systems.  He suggested the use of genetic algorithms for test generation, and developed the technique of “native-mode self-test” in which instruction sequences residing in memory are used as tests for faults in complex processors.  He also developed techniques for testing analog/mixed-signal circuits and designs of on-chip circuits for facilitating the tests.

He has published extensively, has received many “best paper” awards, and is included in the ISI list of “highly-cited” researchers.  He has supervised more than 90 Ph.D. dissertations and is particularly proud of the accomplishments of his students, many of whom hold senior positions in academia and industry. He has been elected Fellow of the IEEE as well as Fellow of the ACM, and is the recipient of the 2005 IEEE Emanuel R. Piore Award.

Janak Patel (U Illinois at Urbana Champaign, USA) is a Professor Emeritus of Electrical and Computer Engineering at the University of Illinois.
Patel’s research contributions include Pipeline Scheduling, Cache Coherence, Cache Simulation, Interconnection Networks, On-line Error Detection, Reliability analysis of memories with ECC and scrubbing, Design for Testability, Built-In Self-Test, Fault Simulation and Automatic Test Generation. Patel has supervised over 85 M.S. and Ph.D. theses and published over 200 technical papers . He was a founding technical advisor to Nexgen Microsystems that gave rise to the entire line of microprocessors from AMD. He was a founder of successful startup, Sunrise Test, a CAD company for chip testing, now owned by Synopsys.

He received a Bachelor of Science degree in Physics from Gujarat University, India and Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology, Madras, India, and a Master of Science and Ph.D. in Electrical Engineering from Stanford University. He is a fellow of ACM and IEEE and a recipient of the 1998 IEEE Piore Award.

Hans-Joachim Wunderlich (U Stuttgart, Germany). Besides skiing, hiking and mountain-biking, Hans-Joachim Wunderlich has been active in the areas of test, design, and fault tolerance for more than 30 years. He is the head of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart, Germany. Hans-Joachim Wunderlich is the author and co-author of more than 250 articles and a fellow of IEEE.