Room: Florentine II
Organizer: Suriyaprakash Natarajan, Intel, and John Carulli, GlobalFoundries
Moderator: Li-C. Wang, University of California, Santa Barbara

Abstract: Modern IC design and manufacturing have progressed in leaps and bounds, resulting in unimaginable integration, and power-performance advancements. This progress has been accompanied by adverse design-layout-process interactions and increased defect sensitivity. Controlling these complex interactions has exacted a steep price in terms of delaying yield ramp, extending silicon validation to characterize and fix marginal effects, and test screening being overwhelmed in time and volume to be able to ensure outgoing customer quality. There is, however, a bright side. Each step of the manufacturing, validation and test process generates information. This information, if effectively organized and analyzed, has the potential to result in efficiency and quality improvements that parallel in scale to the manufacturing process itself. Recent developments in data analytics methods have enabled harnessing of this information towards some benefits, while promising much more. This panel will explore major problems that can potentially be solved with advanced analytics, and also current solutions in the market targeted at some of these problems. Experts from integrated and fabless design houses will present their perspective on problems they encounter, while vendors of EDA solutions on data analytics will shed light on the nature of problems solved by current methods and those that will be addressed by solutions to come.

• Panel Members:
  • Gil Levy (Optimal+)
  • Dirk De Vries (Qualtera)
  • John Kim (Synopsys)
  • Amit Nahar (Texas Instruments)
  • Abhijit Sathaye (Intel)