Room: Florentine III
Organizer: T.M. Mak (Independent)
Moderator: Kun Young Chung, U C San Diego

• HBM Test challenges in 2.5D ASIC/SIP
  Krishnamoorthy Balachandran (Cisco, USA)
• 2.5D Integration Test Challenges for SoC Designs
  Jon Colburn (nVidia, USA)

  Abstract: The increased device integration available with 2.5D manufacturing provides a number design benefits, including smaller footprint, lower power and higher bandwidth connections. However it also comes with an interesting set of test challenges for complex SoC designs that need to be understood and addressed early in the DFT planning process.

• A functional reliability test vehicle to study system reliability of 3D IC device.
  Ganesh Hariharan (Xilinx, USA)