Tutorial 3 – Understanding the Unique Fallout From Cell Aware Tests

Organizer & Instructor: Adit Singh (Auburn University)

Adit Singh (Auburn University)

Adit Singh (Auburn University)


Show Bio.
Adit D. Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, where he directs the VLSI Design and Test Laboratory. His technical interests span all aspects of VLSI test and reliability. He has published over two hundred research papers, served as a consultant for several major semiconductor companies, and holds international patents that have been licensed to industry. He has held leadership roles at dozens of international test conferences and also serves on the editorial boards of IEEE Design and Test Magazine, and JETTA. He has served (2007- 11) as Chair of the IEEE Test Technology Technical Council (TTTC), and (2011-2015) on the Board of Governors of the IEEE Council on Design Automation (CEDA). He is a Fellow of IEEE, a Golden Core member of the IEEE Computer Society.
 

Summary

Cell Aware testing has received much publicity over the past couple of years, with several reported success stories in screening defects missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part despite industrial strength stuck-at and 5-detect TDF testing. Significant additional fallout from cell aware tests has also been reported for automotive parts already screened to stringent “zero-defect” standards. Importantly, the vast majority of these test escapes were observed to cause failure in actual system application, pointing to a serious field reliability issue. This raises some important questions: What are these new defects that are being detected by cell aware tests? Why are they missed by traditional stuck-at and TDF testing? For what applications are these test escapes a real problem? Why has this problem only recently been discovered? Can traditional cell unaware test generation be enhanced to detect these faults? This tutorial presents a detailed study of the cell aware test generation methodology to answer these questions. The aim is not only to analyze and understand the defects in modern standard cell libraries missed by traditional tests that are uniquely covered by this new test approach, but also which of these test escapes necessarily need cell layout information for detection, and which can be systematically targeted in a layout unaware manner by enhanced stuck-at and two-pattern test generation.