Organizers:
Dr. Yu Huang (Mentor Graphics)
Show Bio.
Graphics. His research interests include VLSI SoC testing, ATPG, compression and diagnosis. He holds 13 US patents and has 9 patents pending. He has published more than 100 papers on leading IEEE Journals, conferences and workshops. He is a senior member of the IEEE. He has served as technical program committee member for DAC, ITC, ATS, ETS, ASPDAC, NATW and some other conferences and workshops in the testing area.
Dr. Wu-Tung Cheng (Mentor Graphics)
Show Bio.
Mr. Wu Yang ((Mentor Graphics))
Show Bio.
of experience in DFT, testing, diagnosis and yield analysis. Mr. Yang is a frequent contributor to many papers and articles for different conferences and magazines. He holds a master degree in Electrical Engineering from Portland State University.
Instructors
Summary
Delivering a stable high yield product on time is the ultimate goal for the semiconductor industry. Reaching this goal becomes more and more difficult, especially when cell internal defects become prevelant. The main challenges in the yield analysis process are to identify the systematic issues, find their root causes and select associated devices with the identified systematic defects for further validation by physical failure analysis. This tutorial discusses the methodologies that improve yield of digital semiconductor devices through scan-based test, volume diagnosis and diagnosis driven yield analysis (DDYA). This gives engineers who work on yield improvement a very fast and highly effective way of defect localization and identification, complementing their traditional and hardware-based methods.