Room: Florentine III
Organizer: Vivek Chikermane Cadence
Moderator:  Vivek Chikermane Cadence

This advanced industrial practices session will focus on advanced defect modeling techniques such as cell-aware testing. Our presenters are thought leaders in their companies which are leaders in designing and manufacturing high volumes of chips in the sub 16 NM technologies and have to constantly improvise to push for higher quality and shrink test cost at the same time

• Jon Colburn (nVidia)
• Srikanth Venkataraman (Intel)
• Sajjad Pagarkar (Qualcomm Technologies)