Room: Florentine III
Organizer: Rohit Kapur, Synopsys
Moderator: Gurgen Harutyunyan (Synopsys)

• ATPG Redefined
  Mark Kassab (Mentor Graphics, USA)

  Abstract: Logic test has evolved dramatically over the past 15 years to keep up with growing design sizes, more complex design styles, new defect mechanisms, and challenging market requirements. We look at the key developments, focusing on the state-of-the-art methodologies in use within the industry, and what is coming next.

• Structural Testing and Its Impact on Product Quality and Diagnostics
  Ramesh Tekumalla (Broadcom, USA)

   

• ATPG: An Essential Building Block for EDA Applications
  Vivek Chickermane (Cadence, USA)

  Abstract: The underlying algorithms used for ATPG were initially focused on sensitizing faults from primary inputs and propagating fault effects with the goal of maximizing fault coverage. Over the years ATPG algorithms have matured to a point where they are being commercially used in many applications outside of test generation. Logic synthesis tools extensively use ATPG to identify and remove redundant logic and then perform additional logic optimization. Identification of false timing paths and other timing analyses are integral to Static Timing Analysis (STA). Formal verification uses a battery of satisfiability algorithms including ATPG to prove logic equivalence between the RTL design and the gate-level implementation. Another example is Clock domain crossing (CDC) analysis and SDC optimization. This presentation will describe the evolution of ATPG from its traditional use model to broad deployment across digital system design automation.