Room: Florentine III
Organizer: Peter Sarson (ams AG)
Moderator: Hans Manhave (Ridgetop, Belgium)

• Test Development : Getting to 0ppm
  Peter Sarson (ams AG)

  Abstract: Into on how to add defect based tests to a Semiconductor Test Program that are intended to find defects rather than prove the performance of the device. This talk will go into details of basic IDD tests through to IDDq analog and delta tests. It will be demonstrated how to use the above mentioned technique with high voltage stress to remove HTOL failures. The talk will also go into parametric side of digital with IDDq delta and low voltage digital testing to other types of defects not usually found with standard testing.

• Analog Fault Simulation
  Robert van Rijsinge (NXP)

  Abstract: “Intro on analog fault simulation followed by experiences using this method on some of NXP’s products. The method enhances fault coverage for analog products but can also serve as a way to find redundant tests, i.e. reduce the test set and hence reduce test time. Another use case is for finding “hidden” systematic yield issues or use to locate root-causes for failing products. “

• Defect Based Testing
  Stefan Vock (Infineon)

  Abstract: “How to enable structural defect-oriented analog test? Electronic devices have become a vital part of and influence in modern life. Advancing semiconductor and packaging technologies are rapidly evolving, enabling exponential growth in functionality within a device. Additionally, the quality and reliability requirements towards semiconductors accelerate tremendously. Thus, unfolding a new level of challenges for production testing. Therefore, an approach about how we, the semiconductor testing community, could achieve high quality reliability production testing at reasonable cost will be proposed. “