Room: Florentine I
Moderator: Alberto Bosio (LIRMM, France)

• A Programmable Method for Low-Power Scan Shift in SoC Integrated Circuits
  Ran WANG (Duke University), Bonita BHASKARAN (NVIDIA Corp.), Karthikeyan NATARAJAN (Nvidia), Kaushik NARAYANUN (NVIDIA Corp.), Ayub ABDOLLAHIAN (Nvidia), Krishnendu CHAKRABARTY (Duke University), Amit SANGHANI (Nvidia)
• Dynamic Clocking Architecture for Concurrent Testing and Peak Power Reduction
  Milind SONAWANE (NVIDIA), Pavan Kumar DATLA JAGANNADHA, Karthikeyan NATARAJAN, Sailendra CHADALAVADA, Shantanu SARANGI, Mahmut YILMAZ, Amit SANGHANI (Nvidia)
• Impact of Crosstalk and Process Variation on Capture Power Reduction for At-Speed Test
  Surya PIPLANI (STMicroelectronics Pvt. Ltd.), G.S VISWESWARAN (Indraprastha Institute of Information Technology (IIIT), Delhi), Anshul KUMAR (Indian Institute of Technology (IIT), Delhi)