Room: Florentine III
Organizer: Paolo Bernardi (Polito) and Alberto Bosio (LIRMM)
Moderator: Paolo Bernardi (Polito) and Alberto Bosio (LIRMM)

• Evoking Intermittent Resistive Faults by Means of On-Chip Temperature Cycling
  Alireza Rohani, CTIT-TDT, University of Twente, The Netherland

  Abstract: One category of No Failures Found (NFF) are intermittent resistive faults (IRFs). Field research has indicated the existence of these faults, and they have also occurred in 3-D TSV chips. These instable interconnection faults are known to be extremely difficult to detect, as they occur random in time. Enhancing the probability of occurring, automatically eases the detection. The cracks and voids in these interconnections could be activated by locally introducing high-speed temperature cycles (ambient to 120 degrees centigrade and v.v.). The presentation will show some initial results.

• Thermal Instability – New Challenge for Manufacturing Test and System Operation of highly integrated VLSI Devices
  Rudolf Strasser, Juergen Alt, Andreas Leininger, Christian Pacha, Wolfgang Molzer (INTEL Germany)

  Abstract: Highly integrated VLSI systems in state of the art technologies — implemented in technologies like 28nm and below — introduce thermal integrity challenges during system operation and manufacturing test. The combination of an increasing set of features at constant cost, higher SOC integration, and realization in nano- scale technologies, creates power densities leading to substantial device self-heating even at constrained power budgets of mobile devices. We present the impact of the temperature dependence of consumed power as well as implications on system stability at elevated temperatures. A simple yet powerful thermal model is outlined and critical power limits are explained and illustrated on this basis. The key contributing factors are highlighted and, based on that, strategies and concepts for robust test and system operation are sketched.

• Chip Surface Temperature distribution estimation for functional programs to be used along TDBI of automotive microcontrollers
  Alessandro Motta, Alberto Pagani (STMicroelectronics, Italy), Paolo Bernardi, Riccardo Cantoro (Politecnico di Torino, Italy)

  Abstract: High reliability standards are required by automotive manufacturer that ask their electronic suppliers to guarantee a defect level lower than 1ppm. Thus, a major goal is to screen out defective parts in the earliest stages of production, anyhow before a defective device reaches the customer. Test During Burn-in (TDBI) plays a key role during back-end phase because it is aimed to give rise to infant mortalities (early life latent failures); It is a process during which electronic components are exposed to high temperatures in a climatic chamber prior to being placed in service, and devices that stop working at this step are discarded. The usage of functional programs for stress and test purposes along TDBI is a recognized methodology for adding a dynamic temperature component to the static contribution of the climatic chamber. We present a temperature modeling methodology able to quickly predict the surface temperature under the execution of a functional program based only on logic simulation on the gate level of the device. Experimental results gathered on a 32-bit automotive microcontroller by using a thermo-camera demonstrates that the estimated temperature distribution strongly correlates with the real measurement.