Room: Florentine II
Organizer: Giorgio Di Natale, (LIRMM) and Ozgur Sinanoglu (NYU Abu Dhabi)
Moderator: Giorgio Di Natale, (LIRMM) and Ozgur Sinanoglu (NYU Abu Dhabi)

• Security Primitives (PUF and TRNG) with STT-MRAM
  Elena Ioana Vatajelu (Politecnico di Torino), Giorgio Di Natale (LIRMM), Paolo Prinetto (Politecnico di Torino)

  Abstract: The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Inner properties of STT-MRAMs make them suitable for the implementation of basic security primitives such Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs). PUFs are emerging primitives used to implement low-cost device authentication and secure secret key generation. On the other hand, TRNGs generate random numbers from a physical process. We will show how it is possible to exploit (i) the high variability affecting the electrical resistance of the magnetic device to build a robust, unclonable and unpredictable PUF, and (ii) the stochastic nature of the write operation in the magnetic device to generate randomly distributed numbers.

• Security of Emerging Non-Volatile Memories: Attacks and Defenses
  Yier Jin (University of Central Florida)

  Abstract: Emerging Non-Volatile Memory (NVM) devices show promise as alternatives to DRAM and SRAM. Phase Change Memory (PCM) is an alternative to DRAM, and Spin Transfer Torque (STT) devices are considered as replacements for last level caches. While these devices possess high density, reduced power consumption, and non- volatility, they come with several security vulnerabilities that could potentially undermine the benefits. Attackers may exploit these vulnerabilities to gain unauthorized access or tamper with sensitive information stored in these devices. In this paper, we describe various attacks that can be launched on emerging NVMs to steal data. These include attacks that require physical presence of an adversary (attacks that apply a magnetic field or a heat gun) to tamper with data, as well as attacks that can be launched by executing malicious programs that surreptitiously generate malicious writes to accelerate device wear out. Next, we survey existing defenses to ensure data confidentiality (techniques that use standard cryptographic algorithms as well as techniques that leverage inherent properties of these devices to encrypt/ decrypt data), integrity (error correcting codes and circuit-microarchitecture co-design approaches), and availability (wear leveling algorithms and other microarchitecture approaches). This paper provides a comparative discussion of their advantages and disadvantages.

• Thwarting Timing Attacks on NEMS Relay Based Designs.
  Samah Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu (NYU Abu Dhabi)

  Abstract: NEMS relay technology is a promising class of emerging devices that offer zero static leakage and hence overcomes the power dissipation issues of deep-submicron CMOS technology devices. As NEMS relay based digital circuits have potentially higher energy-efficiency than those based on CMOS transistors, circuits based on NEMS relay device are worth exploring. However, NEMS relay devices suffer from large delay compared to CMOS technology; Binary Decision Diagram (BDD) based implementation targets to minimize the total circuit delay, fixing this problem. However, such an implementation renders the timing delay of a NEMS based circuit input-dependent, which can be exploited to infer on-chip secret information from delay information. In this presentation, we illustrate these security vulnerabilities and present countermeasures for cipher designs that have an on-chip secret key that needs to be protected.