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Monday, May 4th, 2009
8:00am-9:00am Breakfast
9:00am-11:00am Plenary Session
| Welcome message: | Magdy Abadir, General Chair |
| Program Introduction: | Cecila Metra, Program Chair |
| Keynote Speaker: | J. Kibarian, President & CEO, PDF Solutions |
| Invited Keynote: | "Testing New Generation of Multifunctional Embedded Microsystems", B. Kaminska (Canadian Researcher Chair), Simon Fraser (Univ. Canada) |
| Awards Presentation: |
IEEE Fellow Awards
TTTC Most Successful Technical Meeting Award
TTTC Most Populous Technical Meeting Award
VTS 2008 Best Paper Award
VTS 2008 Best Panel Award
VTS 2008 Best Innovative Practices Award
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11:00am-11:30am Break
11:30am-12:30pm Sessions 1
Session 1A: Microprocessor Test
Moderator: F. Lombardi (Northeastern Univ., USA)
- Efficient Array Characterization in the UltraSPARC T2
Tom ZIAJA (Sun MicroSystems Inc.), Poh TAN (Sun MicroSystems Inc.)
- Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller
Michail MANIATAKOS (Yale University, USA), NAGHMEH KARIMI (University of Tehran - Iran), Chandrasekharan TIRUMURTI (Intel Corporation - USA), Abhijit JAS (Intel Corporation - USA), Yiorgos MAKRIS (Yale University - USA)
- Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells
JIN-FU LI (National Central University - Taiwan), Yu-Jen HUANG (National Central University - Taiwan), Yone-Jyun HU (National Central University - Taiwan)
Session 1B: Fault Models
Moderator: H.-J. Wunderlich (Stuttgart University, Germany)
- An Electrical Model for the Fault Simulation of Small-Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
Nicolas HOUARCHE (LIRMM - France), Alejandro CZUTRO (U Freiburg - Germany), Mariane COMTE (LIRMM - Univ. of Montpellier - France), Piet ENGELKE (University of Freiburg - Germany), Ilia POLIAN (University of Freiburg - Germany), Bernd BECKER (University of Freiburg - Germany), Michel RENOVELL (LIRMM - France)
- Small Delay Fault Model for Intra-Gate Resistive Open Defects
MASAYUKI ARAI (Tokyo Metropolitan University - Japan), Akifumi SUTO (Tokyo Metropolitan University - Japan), KAZUHIKO IWASAKI (Tokyo Metropolitan University - Japan), Katsuyuki NAKANO (Semiconductor Technology Academic Research Center - Japan), Michihiro SHINTANI (Semiconductor Technology Academic Research Center - Japan), Kazumi HATAYAMA (Semiconductor Technology Academic Research Center - Japan), Takashi AIKYO (Semiconductor Technology Academic Research Center - Japan)
- Defect Detection Differences between Launch-Off-Shift and Launch-Off-Capture in Sense-Amplifier-Based Flip Flop Testing
Haluk KONUK (Broadcom Corp - USA)
IP Session 1C: Design and Test Practices and Trends in East Asia
| Organizer: | C. W. Wu (Natioanl Tsing Hua Univ., Taiwan) |
| Moderator: | W.-H. Wang (Intel) |
| Presenters: |
H.-P. Lin (Farady): "Design and Test Practices and Trends, from the Perspective
of FTC"
J. Lai (Global Unichip): "Design and Test Practices and Trends, from the Perspective
of GUC"
K.-C. Chang (Richtek Technology): "Design and Test Practices and Trends, from the
Perspective of Richtek" |
12:30pm-2:15pm Lunch
TTTC Service Awards presentation cerimony will take place at lunch
venue between 1:00pm and 2:15pm
2:15pm-3:15pm Sessions 2
Session 2A: Robust Design and Fault Tolerance
Moderator: P. Prinetto (Politecnico di Torino, Italy)
- Soft-Error Hardening Designs of Nanoscale CMOS Latches
Sheng LIN (Northeastern Univ. - USA), Yong-Bin KIM (Northeastern Univ. - USA), Fabrizio LOMBARDI (Northeastern University - USA)
- Exploiting Unused Spare Columns to Improve Memory ECC
Rudrajit DATTA (University of Texas at Austin - USA), Nur TOUBA (University of Texas at Austin - USA)
- An Adaptive-Rate Error Correction Scheme for NAND Flash Memory
Te-Hsuan CHEN (National Tsing Hua University - Taiwan), YU-YING HSIAO (National Tsing Hua University - Taiwan), Yu-Tsao HSING (National Tsing Hua University - Taiwan), Cheng-Wen WU (National Tsing Hua University - Taiwan)
Session 2B: Delay Fault Testing I
Moderator: V. Agrawal (Rutgers Univ., USA)
- Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric
Zheng WANG (Texas A&M University - USA), Duncan Moore Henry WALKER (Texas A&M University - USA)
- Recursive Path Selection For Delay Fault Testing
Jaeyong CHUNG (University of Texas at Austin - USA), Jacob ABRAHAM (University of Texas - USA)
- A Synthesis Method to Alleviate Over-testing of Delay Faults Based on RTL Don't Care Path Identification
Yuki YOSHIKAWA (Hiroshima City University - Japan), Satoshi OHTAKE (Nara Institute of Science and Technology - Japan), Tomoo INOUE (Hiroshima City Univ. - Japan), Hideo FUJIWARA (Nara Institute of Science and Technology - Japan)
IP Session 2C: ATE Vision 2020: New Frontiers for ATEs
| Organizer: | A. Koche (Verigy) |
| Moderator: | A. Koche (Verigy) |
| Presenters: |
R. Barth (ITRS): "Test Challenges of Device Scaling"
A. Crouch (Asset-Intertech): "The ATE Inside"
C. Ritchie (Verigy): "Getting the Inside Story"
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3:15pm-3:45pm Break
3:45pm-4:45pm Sessions 3
Session 3A: Debug
Moderator: Z. Navabi (Northeastern Univ., USA)
- Automated Selection of Signals to Observe for Efficient Silicon Debug
Joon-Sung YANG (University of Texas at Austin - USA), Nur TOUBA (University of Texas at Austin - USA)
- A New Post-silicon Debug Approach Based on Suspect Window
GAO JIANLIANG (ICT - China), Xiaowei LI (Chinese Academy of Sciences - China), Yinhe HAN (Chinese Academy of Sciences - China)
- Debug of Speed Path Failures Using Functional Tests
Srikanth VENKATARAMAN (Intel Corporation - USA), Richard MCLAUGHLIN (Intel Corp - USA)
Session 3B: Delay Fault Testing II
Moderator: M. Breuer (Univ. of Southern California, USA)
- Output Hazard-Free Transition Delay Fault Test Generation
Sreekumar MENON (AMD - USA), Adit SINGH (Auburn University - USA), Vishwani AGRAWAL (Auburn University - USA)
- Efficient scheduling of path delay tests for latch-based circuits
KUN YOUNG CHUNG (Samsung Electronics Co., Ltd. - Korea), Sandeep GUPTA (University of Southern California - USA)
- Effective and Efficient Test Pattern Generation for Small Delay Defects
SANDEEP GOEL (LSI Corporation - USA), Narendra DEVTA-PRASANNA (LSI Corporation - USA), Ritesh TURAKHIA (LSI Corporation - USA)
IP Session 3C: Industrial Approaches for Quality and Compression
| Organizer: | Y. Sato (Kyushu Institute of Technology, Japan) |
| Moderator: | M. Arai (Tokio Metropolitan University, Japan) |
| Presenters: |
Y. Onozaki, T. Hasegawa, S. Fujita (Toshiba), D. Martin, T. Ayres (Synopsys): "Test
Quality Improvement with Synchronized On-Chip Clocking"
M. Sato, T. Hasegawa, K. Tsutsumida, Y. Sato (Hitachi), V. Chickermane, A. Uzzaman,
P. Zhang (Cadence):
"Harmonious BIST: A DFT Approach to Higher Test Coverage and
Higher Compression Ratio"
P. Mantri, M. Gala (Sun Micro): "Logic Depth, Test data Volume & Defects Per Million
(DPM): A case study of Ultrasparc T2 SoC Multi-core Microprocessors"
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8:00pm-9:00pm Sessions 4
Session 4A: Panel: Apprentice - VTS Edition: Season 2
| Organizer: | Kee Sup Kim (Intel) |
| Moderator: | Kee Sup Kim (Intel) |
| Panelists: | A. Crouch (Asset-Intertech), A. Gattiker (IBM), S. Ozev (Arizona State Univ., USA), B. Cory (NVidia), R. Kapur (Synopsys) |
Session 4B: Panel: DFT and Test Problems from the Trenches
| Organizer: | H. Konuk (Broadcom Corporation) |
| Moderator: | H. Konuk (Broadcom Corporation) |
| Panelists: | Z. Conroy (Cisco), B. Corey (Nvidia), R. Aitken (ARM) |
Session 4C: Student Posters
| Organizers: | Y. Makris (Yale Univ., USA), H. Stratigopoulos (TIMA, France) |
| Moderator: | H. Stratigopoulos (TIMA, France) |
Tuesday, May 5th, 2009
7:30am-8:30am Breakfast
8:30am-9:30am Sessions 5
Session 5A: Diagnosis
Moderator: J. Ferguson (Univ. of California Santa Cruz, USA)
- Multiple-Fault Silicon Diagnosis Using Faulty-Region Identification
Meng-Jai TASI (National Chiao Tung University - Taiwan), Chia-Tso CHAO (National Chiao Tung University - Taiwan), Jing-Yang JOU (National Chiao Tung University - Taiwan), Meng-Chen WU (National Chiao Tung University - Taiwan)
- Predictive Test Technique for Diagnosis of RF CMOS Receivers
Kay SUENAGA (University of Balearic Islands - Spain), Rodrigo PICOS (University of Balearic Islands - Spain), SEBASTIAN BOTA (Universitat de les Illes Balears - Spain), eugeni ISERN (University of Balearic Islands - Spain), Eugeni GARCIA MORENO (University of Balearic Islands - Spain), Miquel ROCA (University of Balearic Islands - Spain)
- Controlling DPPM through Volume Diagnosis
Xiaochun YU (Carnegie Mellon University - USA), Yen-Tzu LIN (Carnegie Mellon University - USA), Ronald Shawn BLANTON (Carnegie Mellon University - USA)
Session 5B: Delay Fault Testing and Signal Integrity
Moderator: X. Li (Chinese Academy of Science, China)
- Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions
Edward FLANIGAN (Southern Illinois University - USA), Spyros TRAGOUDAS (Southern Illinois University - USA), Arkan ABDUL RAHMAN (Southern Illinois University - USA)
- A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost
zhen CHEN (Tsinghua University - China), Dong XIANG (Tsinghua University - China), Boxue YIN (Tsinghua University - China)
- A High-level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections
SUNGHOON CHUN (Yonsei University - Korea), Yongjoon KIM (Yonsei University - Korea), Taejin KIM (Yonsei University - Korea), Sungho KANG (Yonsei University - Korea)
IP Session 5C: Yield and Marginalities
| Organizer: | R. Aitken (ARM) |
| Moderator: | R. Aitken (ARM) |
| Presenters: |
A. Gattiker (IBM): "Trading Off Margin vs. Yield: Is What We Model What We Get?"
C. E. Lew (Qualcomm): "Process Variability-Induced Timing Failures"
Z. Conroy (Cisco): "Can You Blame System Fails On Low Margin?"
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9:30am-10:00am Break
10:00am-11:00am Sessions 6
Session 6A: YIELD
Moderator: S. Bernard (LIRMM, France)
- False Path Aware Timing Yield Estimation Under Variability
Lin XIE (University of Wisconsin Madison - USA), Azadeh DAVOODI (University of Wisconsin Madison - USA), Kewal SALUJA (Univ. of Wisconsin Madison - USA), Abhishek SINKAR (University of Wisconsin Madison - USA)
- Bridging DFM Analysis and Volume Diagnostics for Yield Learning
Mark WARD (LSI Corporation - USA), SANDEEP GOEL (LSI Corporation - USA), Brady BENWARE (Mentor Graphics - USA), Ritesh TURAKHIA (LSI Corporation - USA)
- Yield and Cost Analysis of a Reliable NoC
Saeed SHAMSHIRI (UCSB - USA), KWANG-TING CHENG (UC Santa Barbara - USA)
Session 6B: BIST
Moderator: S. Hellebrand (Univ. of Paderborn, Germany)
- Restrict Encoding for Mixed-Mode BIST
Abdul-Wahid HAKMI (University of Stuttgart - Germany), Stefan HOLST (Universitaet Stuttgart - Germany), Hans-Joachim WUNDERLICH (Universität Stuttgart - Germany), Jürgen SCHLöFFEL (Mentor Graphics - USA), Friedrich HAPKE (Mentor Graphics - USA), Andreas GLOWATZ (Mentor Graphics - USA)
- A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset
Keith JENKINS (IBM TJ Watson ResearchCenter - USA), Lionel LI (IBM TJWatson Research Center - USA)
- Experimental validation of a BIST technique for CMOS APS
LIVIER LIZARRAGA (TIMA - France), Salvador MIR (TIMA Laboratory - France), Gilles SICARD (TIMA Laboratory - France)
IP Session 6C: New Practices in Defect-Based Testing
| Organizer: | P. Maxwell (Aptina) |
| Moderator: | P. Maxwell (Aptina) |
| Presenters: |
P.K. Ahuja (Sun Microsystems): "Test for Reliability of Embedded SRAM"
J. Fitzgerald (AMD): "Marginal Defects: Are Power-Only Defects Really Defects?"
H. Manhaeve (QStar): "Dynamic Supply Current Signature (Iddcs) Analysis"
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11:00am-11:30am Break
11:30am-12:30pm Sessions 7
Session 7A:Test and Verification
Moderator: S. Davidson (Sun Microsystems, USA)
- Physically-Aware N-Detect Test Relaxation
Yen-Tzu LIN (Carnegie Mellon University - USA), Chukwuemeka EZEKWE (Carnegie Mellon University - USA), Ronald Shawn BLANTON (Carnegie Mellon University - USA)
- Automatic Selection of Internal Observation Signals for Design Verification
Tao LU (Institute of Computing Technology, CAS - China), HUAWEI LI (Chinese Academy of Sciences - China), Xiaowei LI (Chinese Academy of Sciences - China)
- STDF Memory Fail Datalog Standard
Ajay KHOCHE (Verigy - USA)
Session 7B: Transistor Aging and Power Supply Noise
Moderator: H. Manhaeve (QStar)
- Testing for Transistor Aging
Altug Hakan BABA (Stanford University - USA), Subhasish MITRA (Stanford University - USA)
- Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths
Junxia MA (University of Connecticut - USA), Jeremy LEE (University of Connecticut - USA), Mohammad TEHRANIPOOR (University of Connecticut - USA)
- Understanding Power Supply Droop During At-Speed Scan Testing
Pankaj PANT (Intel - USA), Joshua ZELMAN (Intel - USA)
IP Session 7C: Value of DFM in Volume Diagnosis Arena
| Organizers: | S. K. Goel, M. Ward (LSI Corporation) |
| Moderator: | G. Eide (Mentor Graphics) |
| Presenters: |
R. Aitken (ARM): "Automation in Silicon Characterization"
M. Ward (LSI): "Using Volume Diagnostics and DFM Practices to Drive Yield
Improvement"
S. Venkataraman (Intel): "Tying DFM to Test and Volume Diagnosis"
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12:30pm-1:30pm Lunch
1:30pm-3:00pm Special Sessions 8
Session 8A: New Topic: At-Speed Testing in the Face of Process Variations
| Organizer: | B. Courtois (CMP, France) |
| Moderator: | X. Gu (Cisco) |
| Presenter: | C. Visweswariah (IBM) |
Session 8B: TTTC 2009 Best Doctoral Contest
| Organizers: | Y. Makris (Yale Univ., USA), H. Stratigopoulos (TIMA, France) |
| Moderator: | H. Stratigopoulos (TIMA, France) |
Session 8C: Apprentice Panel Judging Session
| Moderator: | K. S. Kim (Intel) |
3:30pm-10:00pm Social Program
Wednesday, May 6th, 2009
7:30am-8:30am Breakfast
8:30am-9:30am Sessions 9
Special Session 9A: New Topic: Microscale and Nanoscale Thermal
Characterization of Integrated Circuit Chips
| Organizer: | B. Courtois (CMP, France) |
| Moderator: | J. Khare (AMCC) |
| Presenter: | A. Shakouri (Univ. of California at Santa Cruz, USA) |
Special Session 9B: Embedded Tutorial: Quantum Wires, Quantum Wire Arrays:
What are they? Why is anyone ineterested?
And how do you know you have one?
| Moderator: | J. Abraham (Univ. of Texas at Austin, USA) |
| Presenter: | A. Sacco (Northeastern Univ., USA) |
9:30am-10:00am Break
10:00am-11:00am Sessions 10
Session 10A: Test Compaction
Moderator: C.J. Clark (Intellitech Corp., USA)
- Highly X-Tolerant Selective Compaction of Test Responses
Jerzy TYSZER (Poznan University of Technology - Poland), Dariusz CZYSZ (Poznan University of Technology - Poland), Grzegorz MRUGALSKI (Mentor Graphics - USA), Nilanjan MUKHERJEE (Mentor Graphics - USA), Janusz RAJSKI (Mentor Graphics Corporation - USA)
- Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure
Dong XIANG (Tsinghua University - China), Boxue YIN (Tsinghua University - China), KWANG-TING CHENG (UC Santa Barbara - USA), Zhen CHEN (UC Santa Barbara - USA)
- Maintaining Accuracy of Test Compaction through Adaptive Modeling
Sounil BISWAS (Carnegie Mellon University - USA), Ronald Shawn BLANTON (Carnegie Mellon University - USA)
Session 10B: Test and Radiation Test
Moderator: P. Varma (Blue Pearl, USA)
- RT-Level Deviation-Based Grading of Functional Test Sequences
Hongxia FANG (Duke University - USA), Krishnendu CHAKRABARTY (Duke University - USA), Abhijit JAS (Intel Corporation - USA), Srinivas PATIL (Intel Corporation - USA), Chandrasekharan TIRUMURTI (Intel Corporation - USA)
- Analytical Model for Multi-site Efficiency with Clustering, Yield and Parallel to Serial Test Times
Robert DAASCH (Portland State University - USA), Naveen VELAMATI (Portland State University - USA)
- DfT Reuse for Low-Cost Radiation Testing of SoCs: a case study
Paolo BERNARDI (Politecnics Di Torino - Italy), Michelangelo GROSSO (Politecnico di Torino - Italy), paolo RECH (Università di Padova - Italy), Matteo SONZA REORDA (Politecnico Di Torino - Italy), Davide APPELLO (STMicroelectronics - Italy), SIMONE GERARDIN (University of Padova - Italy), Alessandro PACCAGNELLA (University of Padova - Italy)
IP Session 10C: DfT and Test Practices for Power-Managed Low Power Chips
| Organizers: | S. Ravi (Texas Instruments), K. Hatayama (STARC) |
| Moderators: | S. Ravi (Texas Instruments), K. Hatayama (STARC) |
| Presenters: |
S. Ravi , A. Bhat (Texas Instruments): "Manufacturing Test and Silicon Debug Practices
for Power Managed Chips"
H. Iwata, J. Matsushima, Y. Maeda, M. Takakura (Renesas): "The Application of
CooLBIST for a Real Chip"
V. Chickermane (Cadence): "An EDA Perspective on Power Management Test"
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11:00am-11:30am Break
11:30am-1:00pm Sessions 11
Session 11A: Analog Test and Calibration
Moderator: A. Ivanov (University of British Columbia, Canada)
- On-line Calibration and Power Optimization of RF systems using a Built-in Detector
CHAOMING ZHANG (University of Texas at Austin - USA), Ranjit GHARPUREY (University of Texas at Austin - USA), Jacob ABRAHAM (University of Texas - USA)
- Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC
Hsiu-Ming CHANG (UCSB - USA), Chin-Hsuan CHEN (UCSB - USA), Kuan-Yu LIN (Industrial Technology Research Institute - Taiwan), KWANG-TING CHENG (UC Santa Barbara - USA)
- A Time Domain Method to Measure Oscillator Phase Noise
Kenneth BLAKKAN (Cypress Semiconductor - USA), Mani SOMA (Univ. of Washington - USA)
- A Packet Based 2-Site Test Solution for GSM Transceivers with Limited Tester Resources
ERDEM ERDOGAN (Duke University - USA), Sule OZEV (Arizona State University - USA)
Session 11B: Emergent Technology and Security
Moderator: J. Tyszer (Poznan University of Technology, Poland)
- Design-for-Testability for Digital Microfluidic Biochips
TAO XU (Duke University - USA), Krishnendu CHAKRABARTY (Duke University - USA)
- Stuck-Open Fault Leakage and Testing in Nanometer Technologies
Victor Hugo CHAMPAC (Istituto Nacional de Astrofisica - Mexico), Julio VAZQUEZ-HERNANDEZ (INAOE - Mexico), Charles HAWKINS (Univ New Mexico - USA), Jaume SEGURA (Univ. des Illes Ballears - Spain)
- SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-Level Security Integration
Dan ZHAO (University of Louisiana at Lafayette - USA), Unni CHANDRAN (University of Louisiana at Lafayette - USA)
- Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA
Gaetan CANIVET (TIMA Laboratory - France), Regis LEVEUGLE (TIMA Laboratory - France), Jessy CLéDIèRES (CEA/LETI - France), Frederic VALETTE (DGA/CELAR - France), Marc RENAUDIN (TIEMPO - France)
1:00pm-2:00pm Lunch
2:00pm-3:30pm Sessions 12
Special Session 12A: Panel: Analog Test and Characterization: The Long Road
To Realization
| Organizer: | A. Sinha (AMD) |
| Moderator: | V. Ganti (AMD) |
| Panelists: | G. Roberts (McGill Univ. Canada), J. Macri (AMD), M. D'Abreau (Sandisk), S. Sunter (LogicVision) |
Special Session 12B: Panel: SoC Power Management Implications on Validation
and Testing
| Organizer: | B. Kapoor (MIMASIC) |
| Moderators: | S. Tabatabaei (SiTime), E. Sperling (System-Level Design) |
| Panelists: | B. Kapoor (MIMASIC), V. Srinivas (Synopsys), S. Verma (Conexant), H. Mahmoodi (SFSU), R. Aitken (ARM) |
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