Monday, April 27, 2026

7:30 AM - 8:30 AM Registration

Grand Foyer

8:30 AM - 9:00 AM Plenary Session - Welcome by the Chairs & Awards

Grand Ballroom

9:00 AM - 10:00 AM Opening Keynote

Grand Ballroom

Chair: Naghmeh Karimi (University of Maryland Baltimore County)

Rafic Makki, Ph.D.
Head Technologist
Executive Director
Mubadala Capital Ventures

Title: World Models - The Next Big Leap

Abstract: World models are emerging across applications ranging from humanoid robotics to healthcare and drug discovery. They represent a fundamental shift from next token prediction to next state prediction. This talk provides an overview of some of the most impactful innovations in this space and the implications on compute and hardware security.

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10:00 AM - 10:30 AM Break

10:30 AM - 11:30 AM Regular Session 1: "Machine Learning for Test and Security"

Room 1 (Merlot & Syrah)

Chair: Maksim Jenihhin (Tallinn University of Technology)

A Physics-Informed Machine Learning Framework for Electromigration Time-to-Failure Prediction
Saeid Karimpour, Emmanuel Nti Darko, Kelvin Tamakloe, Degang Chen (Iowa State University)

WaferIntel: A Lightweight, Sme-Driven Framework for Advanced Defect Pattern Analysis
Dmitri Kalashnikov, Jianqiao Huang, Yan Pan (Microsoft)

Walet: Shap-Guided Classification of Wafer-Level E-Test Variability for Early Process Risk Detection
Ching-Yi Chang (UT Dallas), Matthew Nigh (UC San Diego), John Carulli (Advantest), Yiorgos Makris (UC San Diego)

10:30 AM - 11:30 AM Special Session 1: "Hardware Acceleration for Zero-Knowledge Proof: Recent Advances and Challenges"

Room 2 (Cabernet)

Organizer: Jiafeng Xi (Villanova University)
Chair: Sankaran Menon (Ericsson)

Hardware Acceleration Methodologies for Zero-Knowledge Proof: Existing Challenges and Further Innovations
Jiafeng Xi (Villanova University)

Applying Winograd Bfu for Implementing Ntt with Large Degree and Large Modulus
Debapriya Basu Roy (IIT Kharagpur, India)

Hardware Acceleration Challenges for Quantum-Secure Zero-Knowledge Proofs: A Balanced Design Perspective
Pengzhou He (Auburn University at Montgomery)

10:30 AM - 11:30 AM IP Session 1: "Efficient Multi-die Interconnect Test Architecture & Repair Methods"

Room 3 (Zinfandel)

Organizer: Tapan Chakraborty (Renesas Electronics)
Chair: Vinay Kumar Kotha (Cisco Systems)

Multi-Die Interconnect Test Architecture & Repair Methods
Tapan Chakraborty (Renesas Electronics)

Interconnect Test and Repair Language (ITRL) for Chiplets and 3D IC Packages
Rajesh Pendurkar (Cadence)

Interconnect Defect Modeling for Multi-Die Packages
Jennifer Dworak (SMU)

11:30 AM - 12:30 PM Regular Session 2: "Generative AI for Test, Verification and Security"

Room 1 (Merlot & Syrah)

Chair: David Lerner (Intel Corporation)

DefectVICL: Data-Efficient Wafer Defect Classification with Vision In Context Learning
Md Fahim Ul Islam, Soyed Tuhin Ahmed (Arizona State University), John Carulli (Advantest), Krishnendu Chakrabarty (Arizona State University)

FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
Jiaxin Wan (University of Illinois, Champaign-Urbana), Chia-tung Ho, Yunsheng Bai (NVIDIA), Cunxi Yu (University of Maryland, College Park), Deming Chen (University of Illinois, Champaign-Urbana), Haoxing Ren (NVIDIA)

RTL-Forge: CNF-Anchored, LLM-Assisted Verilog Generation
Prithwish Basu Roy (New York University), Akashdeep Saha (New York University Abu Dhabi), Manaar Alam (New York University Abu Dhabi), Johann Knechtel (NYUAD), Michail Maniatakos (NYU-Ad), Ozgur Sinanoglu (New York University Abu Dhabi), Ramesh Karri (NYU)

11:30 AM - 12:30 PM Special Session 2: "Security in the Era of Quantum Computing"

Room 2 (Cabernet)

Organizer: Samah Mohamed Saeed (City College of New York)
Chair: Kaveh Shamsi (University of Texas at Dallas)

Learning Quantum Algorithm Footprints to Evaluate Circuit Obfuscation
Donald Lushi (City College of New York)

Hardware Acceleration of PQC Standards
Budhi Perera (New York University)

Security Issues in multi-tenant quantum computers
Kanad Basu (Rensselaer Polytechnic Institute)

Timing-Based Forensics for Quantum Hardware
Donald Lushi (City College of New York)

11:30 AM - 12:30 PM IP Session 2: "Applying Analog Scan to Industrial Circuits"

Room 3 (Zinfandel)

Organizer: Steve Sunter (Siemens EDA)
Chair: Lee Harrison (Siemens EDA)

Diverse needs and challenges in achieving practical and effective analog scan
Degang Chen (Iowa State University)

Steps to 95% defect coverage for analog scan
Ashok Mathur (AMD)

Comparing analog scan and digital scan
Steve Sunter (Siemens EDA)

12:30 PM - 2:00 PM Lunch, Ph.D. McCluskey Competition Poster Session, and PhD Forum Poster Session

Pool Patio

Chair: Angeliki Kritikakou (Univ Rennes, Inria, Irisa)

PhD Competition Posters:

From Threats to Trust: Security Strategies for FPGAs and Analog/Mixed-Signal Circuit Design
Jayeeta Chaudhuri (Arizona State University)
Supervisor: Krishnendu Chakrabarty (Arizona State University)

Design and test techniques to enhance analog and mixed-signal (AMS) circuits performance and reliability
Michael Sekyere (Iowa State University)
Supervisor: Degang Chen (Iowa State University)

Automating SoC Security: An End-to-End AI-Assisted Verification and Protection Framework
Sudipta Paria (University of Florida)
Supervisor: Swarup Bhuni (University of Florida)

Manufacturing and In-Field Testing Techniques
Gabriele Filipponi (Politecnico di Torino)
Supervisors: Paolo Bernardi (Politecnico di Torino), Riccardo Cantoro (Politecnico di Torino)

From Components to Architecture: An End-to-End Approach to Soft-Error Tolerance
Michael Rogenmoser (ETH Zurich)
Supervisors: Luca Benini (ETH Zurich), Angelo Garofalo (ETH Zurich), Philippe Sauter (ETH Zurich)

Investigating Hardware for Resilient Artificial Intelligence
Salvatore Pappalardo (Ecole Centrale de Lyon)
Supervisors: Alberto Bosio (Ecole Centrale de Lyon), Bastien Deveautour (Nantes Universite)

Student Forum Posters:

Compiler Technologies for Fault Tolerant Systems
Davide Baroffio (Politecnico di Milano)

Reconfigurable Topology Obfuscation for NoC-Based SoCs: Protecting Designs Against Reverse Engineering
Dipal Halder (University of Florida)

2:00 PM - 3:00 PM Regular Session 3: "Hardware Security and Trust in Heterogeneous Integration"

Room 1 (Merlot & Syrah)

Chair: Adam Cron (Synopsys)

Lead: Link Exploitability Analysis for Die-to-Die Interconnects in Heterogeneous Integration
Arjun Hati (Arizona State University), Ortega Eduardo (ASU), Jonti Talukdar (NVIDIA), James Plusquellic (Univ. of New Mexico), Krishnendu Chakrabarty (Arizona State University)

Rocket: Runtime Operating-Condition Aware KEy Refreshing Technique for Resisting Side-Channel Analysis Attacks
Hasin Ishraq Reefat, Hossein Pourmehrani (University of Maryland Baltimore County), Jean-Luc Danger (Télécom Paris, Institut Polytechnique de Paris), Sylvain Guilley (Secure-Ic / Ltci, Cnrs, Télécom ParisTech / Département d'informatique de l'Ens, Cnrs), Naghmeh Karimi (University of Maryland Baltimore County)

Structural Reconstruction of Analog Circuits Using Graph Neural Networks and Transformers
Dipali Jain (University of Texas at Dallas), Guangwei Zhao (The University of Texas at Dallas), Kaveh Shamsi (University of Texas at Dallas)

2:00 PM - 3:00 PM Special Session 3: "Trustworthy LLMs for Hardware Formal Verification and Reliable Systems"

Room 2 (Cabernet)

Organizer: Hadi Kamali (University of Central Florida)
Chair: Hadi Kamali (University of Central Florida)

Automation of Polynomial Formal Verification using Large Language Models
Luca Muller (University of Bremen/Dfki)

LoRA-Abft: Learnable Algorithmic Fault-Tolerance via Low-Rank Adaptation for Reliable Vllm
Farshad Firouzi (Arizona State University)

From Language to Logic: Bridging LLMs and Formal Representations for RTL Assertion Generation
Hadi Kamali (University of Central Florida)

Exploring Agentic LLM Paradigms for Hardware Verification across Abstraction Levels
Sudipta Paria (University of Florida)

2:00 PM - 3:00 PM McCluskey PhD Competition semi-finals 1

Room 3 (Zinfandel)

Chair: Angeliki Kritikakou (Univ Rennes, Inria, Irisa)

From Threats to Trust: Security Strategies for FPGAs and Analog/Mixed-Signal Circuit Design
Jayeeta Chaudhuri (Arizona State University)
Supervisor: Krishnendu Chakrabarty (Arizona State University)

Design and test techniques to enhance analog and mixed-signal (AMS) circuits performance and reliability
Michael Sekyere (Iowa State University)
Supervisor: Degang Chen (Iowa State University)

Investigating Hardware for Resilient Artificial Intelligence
Salvatore Pappalardo (Ecole Centrale de Lyon)
Supervisors: Alberto Bosio (Ecole Centrale de Lyon), Bastien Deveautour (Nantes Universite)

3:00 PM - 4:00 PM Regular Session 4: "Built-In Self-Test: Digital, Analog and Low-Power"

Room 1 (Merlot & Syrah)

Chair: Jayesh Kumar Pandey (NVIDIA)

Accelerating Analog Test through Firmware-Hardware Driven Parallelism
Krishna Pramod Madabhushi, Ayush Jain, Logan Puckett, William Jahner, Eslam Hag (Medtronic)

Coverage-Aware Scan Chain Reordering under Iso-Power Constraints for Programmable Low-Power LBIST
Yumei Hu, Hairui Cai, Xiangheng Xie (Huazhong University of Science and Technology), Yaning Wang (Huawei Technologies Co., Ltd.), Yu Huang (HiSilicon Technologies Co., Ltd.), Zhipeng Lv, Zhouxing Su (Huazhong University of Science and Technology)

High-Purity, Low-Cost DAC-Based Multitone Waveform Generation for Built-In-Self-Test Applications
Emmanuel Nti Darko, Saeid Karimpour, Degang Chen (Iowa State University)

3:00 PM - 4:00 PM Special Session 4: "Securing Edge AI Hardware: Emerging Attacks and Multi-Layer Defenses with LLM-Assisted Design"

Room 2 (Cabernet)

Organizer: Farshad Firouzi (Arizona State University)
Chair: Andre Ivanov (University of British Columbia)

Can Language Models Secure Hardware? Evaluating Retrieval-Augmented Generation for IP Protection
Soheil Salehi (University of Arizona)

MoD-CiM: A Mixture-of-Defenses Framework Against Power-Hammering Attacks in Multi-Tenant Compute-in-Memory
Farshad Firouzi (Arizona State University)

Large Language Model Agents for Hardware Design and Security Verification: A Survey and AI Accelerator Case Study
Farimah Farahmandi (University of Florida)

Architectural Countermeasures for Memory Access Leakage in Edge LLM Inference on eFPGAs
Hadi Kamali (University of Central Florida)

3:00 PM - 4:00 PM McCluskey PhD Competition semi-finals 2

Room 3 (Zinfandel)

Chair: Angeliki Kritikakou (Univ Rennes, Inria, Irisa)

Manufacturing and In-Field Testing Techniques
Gabriele Filipponi (Politecnico di Torino)
Supervisors: Paolo Bernardi (Politecnico di Torino), Riccardo Cantoro (Politecnico di Torino)

From Components to Architecture: An End-to-End Approach to Soft-Error Tolerance
Michael Rogenmoser (ETH Zurich)
Supervisors: Luca Benini (ETH Zurich), Angelo Garofalo (ETH Zurich), Philippe Sauter (ETH Zurich)

Automating SoC Security: An End-to-End AI-Assisted Verification and Protection Framework
Sudipta Paria (University of Florida)
Supervisor: Swarup Bhuni (University of Florida)

4:00 PM - 4:30 PM Break

4:30 PM - 5:30 PM Embedded Tutorial: "A Primal–Dual Paradigm for Agentic Test Data Analytics"

Room 1 (Merlot & Syrah)

Organizer: Jennifer Dworak (Southern Methodist University)
Chair: Abhijit Sathaye (Intel)

Embedded Tutorial: A Primal–Dual Paradigm for Agentic Test Data Analytics
Li-C Wang (UC Santa Barbara)

Abstract

Recent advances in large language models (LLMs) are transforming how engineers interact with complex data analytics. This talk presents the latest evolution of the Intelligent Engineering Assistant (Iea), an agentic platform developed for semiconductor test data analysis and deployed in an industrial environment.

The system is organized around three components. The first enables engineers to construct analytic workflows by describing analysis steps in natural language. These workflows become reusable "foundation workflows" that capture common patterns of test data analysis. The second component enables workflow fine-tuning, where foundation workflows are automatically adapted to new scenarios by specifying updated conditions or analysis contexts. Executing these workflows generates structured analytic artifacts—collections of descriptive tables that summarize the relevant properties of the data.

The third component enables interactive reasoning over these generated artifacts. Users query the system through natural language, and the agent selects relevant tables and sends them to an LLM for analysis. Because the analytic scope is intentionally constrained to small curated datasets, the LLM can effectively act as a "pseudo-oracle" for interpreting test data.

Together, these components reveal a primal–dual view of test data analytics. The workflow component represents the primal perspective, where analytics is expressed in procedural form. The content-centric reasoning component represents the dual perspective, where analytics emerges from structured data summaries interpreted by LLMs. Workflow fine-tuning bridges these two views by transforming workflows into generators of structured analytic content. This talk discusses the architecture, deployment experience, and lessons learned from applying this primal–dual paradigm to semiconductor test analytics.

Core Message: Workflows generate content; Content enables reasoning.

4:30 PM - 5:30 PM Special Session 5: "Assessment of Security Risks and Defenses in Chiplet"

Room 2 (Cabernet)

Organizer: Naghmeh Karimi (University of Maryland Baltimore County)
Chair: Md Toufiq Hasan Anik

Chiplet from Concept to Silicon
Junie Um (Cadence Design Systems)

360° Overview of Risks when System in Package with Inclusion of Third-Party Chiplets
Sylvain Guilley (Secure Ic, Ltci, Telecom Paris, Institut Polytechnique de Paris)

Feasibility Assessment of Chiplet-to-Chiplet Side Channel Attacks
Naghmeh Karimi (University of Maryland Baltimore County)

4:30 PM - 5:30 PM Regular Session 5: "Memory Test and Repair"

Room 3 (Zinfandel)

Chair: Alessio Antolini (University of Bologna)

An Effective Built-In Self-Test Scheme for Digital Computing-In Memories with MAC Function
Jin-Fu Li, Wen-Ching Liao, Kai-Hsiang Chang (National Central University)

Defect-based Testing for SRAM Address Decoders
Ho-Jie Hsu, Hsien-Chen Lee, Chun-Yu Shen, Po-Tsang Huang (National Yang Ming Chiao Tung University), Shih-Chieh Lin, Yung-Jheng Wang (Realtek Semiconductor Corporation), Ying-Yen Chen (Realtek Semiconductor Corp.), Chien-Yuan Pao, Hung-Yu Lee (Realtek Semiconductor Corporation), Mango Chao (National Yang Ming Chiao Tung University)

Efficient Trimming Test Approach for Stt-MRAMs with Merged Reference Scheme
Jin-Fu Li, Pei-Yun Lin (National Central University)

5:30 PM - 5:45 PM Short Break

5:45 PM - 6:45 PM Panel 1: Predictive Maintenance: Myth or Reality?

Moderator: Vivek Chickermane (Siemens EDA)

Abstract: Silicon Life Cycle Management (SLM) and Predictive Maintenance has received a lot of attention over the past few years. Monitoring for process variations during manufacturing, and to fine-tune operating and performance parameters of a design using on-die monitors has been standard practice for the past few decades. However, predictive maintenance of designs in the field is a relatively new area with very little prior art though it has been standard practice in mechanical/electro-mechanical systems (ex: automotive and aerospace). This panel will focus on practical in-field application of silicon health monitoring with the goal of predicting failures due to silicon degradation, and also techniques to improve availability of designs by taking proactive measures to work around field failures (for example, by repair or by changing the operating environment of a design).

Panelists:
Yervant Zorian (Synopsys)
Nir Sever (proteanTecs)
Vikram Karvat (Movellus)
Mehdi Tahoori (Imec/Kit)

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Tuesday, April 28, 2026

7:30 AM - 8:30 AM Registration

Grand Foyer

8:30 AM - 9:30 AM Keynote 2

Grand Ballroom

Chair: Jennifer Dworak (Southern Methodist University)

Prithviraj Banerjee
Senior Vice President of Innovation
Synopsys

Title: Use of HPC, GPUs and AI/ML in ATPG and Fault Simulation

Abstract: Automatic Test Pattern Generation (ATPG) and Fault Simulation is used to screen for the presence or absence of physical defects or faults in a digital design. The process of ATPG and fault simulation involves a search through all possible input values and can take a very long time. This talk will start with a discussion of early work on using traditional high-performance computing (HPC) for ATPG and fault simulation pursued in academia and industrial research labs. We will then discuss how the latest HPC technologies of GPUs are being applied to speed up ATPG and Fault Simulation. Next, we will discuss how AI/ML is being applied to ATPG, fault simulation and Silicon Lifecycle Management. We will conclude the talk by looking at the future of agentic AI workflows with five levels of autonomy which we call "Reengineering Engineering."

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9:30 AM - 10:00 AM Break

10:00 AM - 11:00 AM Regular Session 6: "Fault Modeling, Simulation and Defect Analysis"

Room 1 (Merlot & Syrah)

Chair: Matteo Sonza Reorda (Politecnico di Torino)

Algorithm-Technology Co-Optimization for Reliable NVM-CAM Systems
Ali Nezhadi, Sina Bakhtavari Mamaghani, Mehdi Tahoori (Karlsruhe Institute of Technology)

Pre-processing Functional And Physical Defect Equivalences To Accelerate Cell-Aware Model Generation
Reza Khoshzaban (Politecnico di Torino), Gianmarco Mongelli, Dorian Ronga (LIRMM), Iacopo Guglielminetti, Michelangelo Grosso (STMicroelectronics s.r.l.), Eric Faehn (STM), Patrick Girard, Arnaud Virazel (LIRMM), Riccardo Cantoro (Politecnico di Torino)

10:00 AM - 11:00 AM Special Session 6: "Reliability Analysis and Hardening of Neural Network for Radiation-Critical Systems"

Room 2 (Cabernet)

Organizer: Luigi Dilillo (University of Montpellier)
Chair: Luigi Dilillo (University of Montpellier)

Reliability Evaluation of Vector-Accelerated Neural Network Inference on a Fault-Tolerant RISC-V SoC for Space Applications
Douglas Almeida dos Santos (University of Montpellier, IES)

Single Event Transient Reliability Analysis & Hardening of NVDLA MAC Unit
Nikolaos Chatzivangelis (University of Thessaly)

Reliability Analysis Framework on NVDLA mapped Dynamic Neural Networks
Nikolaos Zazatis (University of Thessaly / University of Manchester / Ihp Microelectronics)

10:00 AM - 11:00 AM IP Session 3: "Recent Approaches in Dealing with Silent Data Corruption"

Room 3 (Zinfandel)

Organizer: Harish Dattaraya Dixit (Meta)
Chair: Arani Sinha (Intel Corporation)

Resilience approaches in Meta's MTIA Silicon
J. Nithya (Meta)

Deep Functional Test for Reduction of Silent Data Errors in Data Center Processors
David Lerner (Intel)

SDC-oriented Fault Risk Grading in Complex Open Source Out-Of-Order Cores
Francesco Angione (Politecnico di Torino)

11:00 AM - 12:00 PM Regular Session 7: "Reliability and Fault Tolerance in AI Accelerators"

Room 1 (Merlot & Syrah)

Chair: Salvatore Pappalardo (Ecole Centrale de Lyon)

Enfor-Sa: End-to-end Cross-layer Transient Fault Injector for Efficient and Accurate Dnn Reliability Assessment on Systolic Arrays
Rafael Tonneto (Inria), Marcello Traiola (Inria), Fernando Dos Santos (Inria), Angeliki Kritikakou (Univ Rennes, Inria, Irisa)

Ft-Sparse: Algorithm-Based Fault Tolerance for Sparse CNNs Using Structured Sparsity in GPUs
Josie Rodriguez Condia (Politecnico di Torino), Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Jaan Raik (Tallinn University of Technology), Matteo Sonza Reorda (Politecnico di Torino)

A Flexible Framework for Vector Accelerators In-field Testing
Gustavo Vilar De Farias, Josie Rodriguez Condia, Matteo Sonza Reorda, Gustavo Vilar De Farias (Politecnico di Torino)

11:00 AM - 12:00 PM Special Session 7: "Error Correction Techniques For Communication Systems"

Room 2 (Cabernet)

Organizer: Arindam Sanyal (Arizona State University)
Chair: Stephen Sunter (Siemens EDA)

Digital calibration/correction on phase-locked loop
Qiaochu Zhang (University of Virginia)

Machine learning calibration for radios
Arindam Sanyal (Arizona State University)

A gm-C Oscillator-Based On-Chip Offset Test and Calibration Technique for Analog Amplifiers
Tejasvi Das (Rochester Institute of Technology)

11:00 AM - 12:00 PM LBR presentations

Room 3 (Zinfandel)

Chair: Marcello Traiola (Inria)

LBR 1: A Systematic Vulnerability Analysis of Mram-Based Compute-in-Memory against Side-Channel Attacks
Hossein Pourmehrani (University of Maryland Baltimore County), Yashas Krishnamohan, Sumukh Bhanushali, Saurabh Dhiman (Arizona State University), Rajendra Bishnoi (Delft University of Technology), Arindam Sanyal, Farshad Firouzi (Arizona State University), Naghmeh Karimi (University of Maryland Baltimore County)

LBR 2: Close-to-Functional Tests for Two-Cycle Interconnect Faults
Irith Pomeranz (Purdue University)

LBR 3: Compressed Bit-Level Timing-Error Predictors via Binary Neural Networks
Georgios Chatzitsompanis, Nikolaos Kostakis, Georgios Karakonstantis (University of Thessaly)

LBR 4: Confidence-Gap-Driven Functional Test Pattern Generation for Enhancing Functional Safety of CNN Accelerators
Tong-Yu Hsieh, Ching-Hsin Hsu, Wei-Ji Chao (National Sun Yat-sen University)

LBR 5: Diagnostic Test Templates for Two-Cycle Gate-Exhaustive Faults
Irith Pomeranz (Purdue University)

LBR 6: Feature-Aware Trojan Alteration to Evade ML-Based Detection
Lizi Zhang (The University of Wisconsin - Madison), Navid Nader Tehrani, Azadeh Davoodi (University of Wisconsin), Rasit Topaloglu (Adeia)

LBR 7: High-Throughput Metastability Characterization of Arbiters using Hdc-based Bist
Abdullah Sahruri, Martin Margala (University of Louisiana at Lafayette)

LBR 8: New Techniques for Self-Test Library Compaction
Nikolaos Deligiannis, Michelangelo Bartolomucci, Mansour Sohrabian, Riccardo Cantoro, Matteo Sonza Reorda (Politecnico di Torino)

LBR 9: Proton Beam Experiments of Compiler-based Hardware Fault Tolerance
Emilio Corigliano, Davide Baroffio, Federico Reghenzani, Tomas Antonio Lopez, William Fornaciari (Politecnico di Milano)

LBR 10: Test Selection for In-Field Testing Using a Two-Dimensional Aging Space
Irith Pomeranz (Purdue University), Subashini Gopalsamy (Qualcomm Technologies Inc.), Arani Sinha (Intel Corporation), Yonsang Cho (Intel Corporation)

12:00 PM - 1:30 PM Lunch and Late Breaking Results (LBR) Poster Session

Pool Patio

LBR 1: A Systematic Vulnerability Analysis of Mram-Based Compute-in-Memory against Side-Channel Attacks

Hossein Pourmehrani (University of Maryland Baltimore County), Yashas Krishnamohan, Sumukh Bhanushali, Saurabh Dhiman (Arizona State University), Rajendra Bishnoi (Delft University of Technology), Arindam Sanyal, Farshad Firouzi (Arizona State University), Naghmeh Karimi (University of Maryland Baltimore County)

LBR 2: Close-to-Functional Tests for Two-Cycle Interconnect Faults

Irith Pomeranz (Purdue University)

LBR 3: Compressed Bit-Level Timing-Error Predictors via Binary Neural Networks

Georgios Chatzitsompanis, Nikolaos Kostakis, Georgios Karakonstantis (University of Thessaly)

LBR 4: Confidence-Gap-Driven Functional Test Pattern Generation for Enhancing Functional Safety of CNN Accelerators

Tong-Yu Hsieh, Ching-Hsin Hsu, Wei-Ji Chao (National Sun Yat-sen University)

LBR 5: Diagnostic Test Templates for Two-Cycle Gate-Exhaustive Faults

Irith Pomeranz (Purdue University)

LBR 6: Feature-Aware Trojan Alteration to Evade ML-Based Detection

Lizi Zhang (The University of Wisconsin - Madison), Navid Nader Tehrani, Azadeh Davoodi (University of Wisconsin), Rasit Topaloglu (Adeia)

LBR 7: High-Throughput Metastability Characterization of Arbiters using Hdc-based Bist

Abdullah Sahruri, Martin Margala (University of Louisiana at Lafayette)

LBR 8: New Techniques for Self-Test Library Compaction

Nikolaos Deligiannis, Michelangelo Bartolomucci, Mansour Sohrabian, Riccardo Cantoro, Matteo Sonza Reorda (Politecnico di Torino)

LBR 9: Proton Beam Experiments of Compiler-based Hardware Fault Tolerance

Emilio Corigliano, Davide Baroffio, Federico Reghenzani, Tomas Antonio Lopez, William Fornaciari (Politecnico di Milano)

LBR 10: Test Selection for In-Field Testing Using a Two-Dimensional Aging Space

Irith Pomeranz (Purdue University), Subashini Gopalsamy (Qualcomm Technologies Inc.), Arani Sinha (Intel Corporation), Yonsang Cho (Intel Corporation)

1:30 PM - 2:30 PM Panel 2: Automotive Safety Coverage Targets: State of the Art, and the Future

Room 1 (Merlot & Syrah)

Moderator: Srinivas Patil (Qualcomm)

Abstract: The predominant automotive safety standard, Iso 26262, mandates various fault coverage targets to ensure safety for different Automotive Safety Integrity Levels (Asil). However, the Single Point Fault Metric (Spfm) and Latent Fault Metric (Lfm) coverage targets specified by the standard can leave the fault modeling aspects to interpretation. The accepted industry practice is to interpret them as stuck-at fault coverage targets, which are currently achieved using in-field Mbist, LBIST or Software Test Libraries (Stl). The panel of Dft and safety experts will drive the discussion on whether current industry practices are adequate in view of current/future field failure trends and safety requirements, or if we need to target fault models beyond stuck-at which may require new metrics and test methods.

Panelists:
Adam Cron (Synopsys)
Lee Harrison (Siemens)
Adit Singh (Auburn University)
Nirmal Saxena (NVIDIA)

1:30 PM - 2:30 PM Special Session 8: "Reliability Assessment of Dnn Models and Inference on Systolic Arrays"

Room 2 (Cabernet)

Organizer: Maksim Jenihhin (Tallinn University of Technology)
Chair: Jaan Raik (Tallinn University of Technology)

Safpa: Fast analytical reliability assessment for Dnn Inference on Systolic Arrays
Maksim Jenihhin (TalTech – Tallinn University of Technology)

Iterative and Conservative Statistical Fault Injections for Dnn reliability assessments
Matteo Sonza Reorda (Politecnico di Torino)

Flauers: a novel fault injection technique for Systolic Array Accelerated DNNs
Salvatore Pappalardo (Ecole Centrale de Lyon)

1:30 PM - 2:30 PM Regular Session 8: "Emerging Memory Test, Calibration and Reliability"

Room 3 (Zinfandel)

co-Chairs: Rafael Tonetto (Inria), Gabriele Filipponi (Politecnico di Torino)

Temporal Reference Scouting Logic for Pvt Reliable Logic Computation-in-Memory
shanmukha Mangadahalli Siddaramu (Karlsruher Institut für Technologie), Ali Nezhadi (Karlsruhe Institute of Technology), Mahta Mayahinia (Kit university), Sule Ozev (Arizona State University), Mehdi Tahoori (Karlsruhe Institute of Technology)

Variation-Aware Post-Manufacturing Calibration for ReRAM-based Content-Addressable Memory
Haneen G. Hezayyin (Karlsruhe Institute of Technology), Mahta Mayahinia (Kit university), Mehdi Tahoori (Karlsruhe Institute of Technology)

Experimental Validation of Spatial Autocorrelation Framework for RowHammer Test Optimization
Mohammad Farmani, Vineet Suresh Kumar (Florida Polytechnic University)

2:30 PM - 3:30 PM Regular Session 9: "Post-Silicon Validation and Silicon Lifecycle Analytics"

Room 1 (Merlot & Syrah)

Chair: Josie Rodriguez Condia (Politecnico di Torino)

Accelerating Recurring Failure Search With AI-Based Scandump Anomaly Pattern Detection
Lay Wai Kong (AMD)

Track: Telemetry-based Representation Analysis via Centered Kernel Alignment for Silicon Lifecycle Management
Ortega Eduardo (ASU), Jonti Talukdar (NVIDIA), Hsiao-Ping Ni, Krishnendu Chakrabarty (Arizona State University)

Next-Gen Scalable In-System-Test Architecture for NVIDIA Automotive Platform
Sailendra Chadalavada (NVIDIA), Milind Sonawane, Saranyan Sarangan, Alex Hsu, Pavan Javvaji (NVIDIA), Shantanu Sarangi (NVIDIA)

2:30 PM - 3:30 PM Special Session 9: "2.5D/3D Chiplet-based Integration: New Dimensions in Design and Testing"

Room 2 (Cabernet)

Organizer: Jeff Zhang (Arizona State University) and Kevin Cao (University of Minnesota)
Chair: Jeff Zhang (Arizona State University)

Chiplet System Architecture
David Wentzlaff (Princeton University)

Design Automation of 2.5D/3D Chiplet-based Systems
Yu (Kevin) Cao (University of Minnesota)

Design-for-testability of 3D Integrated Circuits
Krishnendu Chakrabarty (Arizona State University)

2:30 PM - 3:30 PM IP Session 4: "AI Applications in Test and Quality"

Room 3 (Zinfandel)

Organizer: Chen He (NXP Semiconductors)
Chair: Chen He (NXP Semiconductors)

AI Application for Test
Prof. Li Peng (UC Santa Barbara)

Agentic-AI based Automation for NXP DFT Flows
Saidapet Ramesh (NXP Semiconductors)

GenAI Application to Silicon Lifecycle Management
Fei Su (Tsinghua University)

3:30 PM - 11:00 PM Social Event

Wine Train

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Wednesday, April 29, 2026

7:30 AM - 8:30 AM Registration

Grand Foyer

8:30 AM - 9:30 AM Keynote 3

Grand Ballroom

Chair: Arani Sinha (Intel Corporation)

Dr. Debendra Das Sharma
Intel Senior Fellow and Chief I/O Architect of Data Center Group, Intel

Title: Architecting the Chiplet Era: Solving Compute, Memory, and Communication Bottlenecks with UCIe®

Abstract: The computing landscape has adopted on-package integration of chiplets to meet the exponential performance demands of applications like AI and HPC. This transition is driven by three critical bottlenecks: the reticle limits of monolithic dies constraining compute scaling, the bandwidth bottleneck with off-package memory; and the power, bandwidth, and latency challenges with communication.

Universal Chiplet Interconnect Express (UCIe®) provides the definitive open standard to solve these, enabling the seamless integration of heterogeneous compute, on-package memory, and communication chiplets. UCIe offers orders of magnitude improvement in bandwidth density, power efficiency, and latency over off-package interconnects with planar and vertical connectivity between chiplets. A unified Security, Manageability, and Debug and Test Architecture (Uda), leverages existing board and rack-level solutions for a seamless user experience. As an open standard, UCIe provides the foundation for power-efficient performance from silicon to the cloud for future computing platforms.

See more details

9:30 AM - 10:00 AM Break

10:00 AM - 11:00 AM Regular Session 10: "ATPG, Scan and Test Compression"

Room 1 (Merlot & Syrah)

Chair: Adit Singh (Auburn University)

C2C: Cell-to-Cell Controllability Evaluation for Partial Scan Selection
Hairui Cai, Zihao Wang (Huazhong University of Science and Technology), Liuzheng Wang, Fei Yang, Mingqi Li (HiSilicon Technologies Co., Ltd.), Lingxiang Liao (Huazhong University of Science and Technology), Yu Huang (HiSilicon Co.), Zhouxing Su, Zhipeng Lv (Huazhong University of Science and Technology)

Scan Chain Reordering for Improving Test Coverage with Compression
Hairui Cai (Huazhong University of Science and Technology), Zezhong Wang (HiSilicon Technologies Co., Ltd), Yu Huang (HiSilicon Co.), Naixing Wang (HiSilicon Technologies Co., Ltd.), Zhouxing Su, Zhipeng Lv (Huazhong University of Science and Technology)

Compact Functional Test Pattern Generation for DNNs Using Evolution Strategies
Tara Gheshlaghi (Karlsruhe Institute of Technology), Dina Moussa (Karlsruhe Institute of Technology), Michael Hefenbrock (Perspix.ai), Mehdi Tahoori (Karlsruhe Institute of Technology)

10:00 AM - 11:00 AM Special Session 10: "Reliable Emerging Electronics in Wearable and Implantable Healthcare Applications"

Room 2 (Cabernet)

Organizer: Sule Ozev (Arizona State University)
Chair: Mehdi Tahoori (Karlsruhe Institute of Technology)

In-situ monitoring of implantable valves through embedded Rf biomechanical signal generator
Jennifer Blain (Arizona State University)

Design of Reliable ADCs for Flexible electronics
Paula Carolina Lozano Duarte (Karlsruhe Institute of Technology)

Excitation and Monitoring Circuit Design for Delay-based Bist of LDOs in Flexible Electronics
Sule Ozev (Arizona State University)

10:00 AM - 11:00 AM IP Session 5: "Recent Developments in IEEE Draft Standards P1687, P1687.2, and P2929"

Room 3 (Zinfandel)

Organizer: Martin Keim (Siemens EDA)
Chair: Tapan Chakraborty (Renesas Electronics)

Developments on IEEE standards 1687
Adam Cron (Synopsys)

Developments on IEEE standard 1687.2
Steve Sunter (Siemens EDA)

Developments on IEEE standard P2929
Sankaran Menon (Ericsson)

11:00 AM - 12:00 PM Regular Session 11: "Test for 3D Integration, Interconnects and Packaging"

Room 1 (Merlot & Syrah)

Chair: Prab Varma (Veda Design Systems Inc.)

Nert: Network- and Routing-aware Testing of Interconnects in Fanout Wafer-Level Packaging
Dhruv Thapar, Partho Bhoumik (Arizona State University), Arjun Chaudhuri (ASU), Krishnendu Chakrabarty (Arizona State University)

Dart: Dynamic Repair for Interconnect Fault Tolerance in Hybrid Bonding
Partho Bhoumik (Arizona State University), Zhichao Chen, Puneet Gupta (University of California, Los Angeles), Krishnendu Chakrabarty (Arizona State University)

Warp-Tpg: Warpage-Aware Test Pattern Generation for Small-Delay Defects
Dhruv Thapar (Arizona State University), Arjun Chaudhuri (ASU), Krishnendu Chakrabarty (Arizona State University)

11:00 AM - 12:00 PM Special Session 11: "Robustness & testability challenges in emerging in-/near-memory computing architectures"

Room 2 (Cabernet)

Organizer: J.-P. Noel (University of Minnesota) and A. Virazel (LIRMM, University of Montpellier)
Chair: Sule Ozev (Arizona State University)

Analysis and Mitigation of Pcm Cells Programming Misalignments in Analog In-Memory Computing Cores
Alessio Antoneli (STMicroelectronics)

Enhancing Testability & Reliability of Near-Memory Computing Architectures through Native Computational Resource Optimization
Lorenzo Campiolini (CEA List)

Enhancing Robustness of Content-Addressable Memories for In-Memory Search
Lui Lui (University of Notre Dame)

11:00 AM - 12:00 PM IP Session 6: "Recent Developments in IEEE Draft Standards 1838, P3164 & Analog Soft Defects"

Room 3 (Zinfandel)

Organizer: Tapan Chakraborty (Renesas Electronics)
Chair: Arjun Chaudhuri (NVIDIA)

Developments on IEEE standards 1838(a)
Adam Cron (Synopsys)

Overview of Accellera / IEEE P3164- Standard for Security Annotation for Electronic Design Integration (SA-EDI)
Sohrab Aftabjahani (Intel)

Marginal Analog Soft Defects: Outlier Kills that Matter
Senthil Singaravelu (Intel)

12:00 PM - 1:30 PM Lunch

Pool Patio

1:30 PM - 2:30 PM Regular Session 12: "SoC Test, Seu Resilience and Silent Data Corruption"

Room 1 (Merlot & Syrah)

Chair: Francesco Angione (Politecnico di Torino)

Iabist: An IJTAG-Compliant Machine Learning-Based Analog Bist Framework for SoC Verification
Jules Kouamo, Emmanuel Simeu (TIMA Laboratory), Michele Portolan (Siemens)

Who Checks the Checker Enhancing Component-level Architectural SeU Fault Tolerance for End-to-End SoC Protection
Michael Rogenmoser (ETH Zurich), Philippe Sauter, Chen Wu, Angelo Garofalo, Luca Benini (ETH Zurich)

Shout - Silent Data Corruption Hunting and Observation Using Transformers
Seyedehmaryam Ghasemi (Karlsruhe Institute of Technology), Shanmukha Mangadahalli Siddaramu (Karlsruhe Institute of Technology), Tara Gheshlaghi (Karlsruhe Institute of Technology), Sani Nassif (Radyalis Llc), Mehdi Tahoori (Karlsruhe Institute of Technology)

1:30 PM - 2:30 PM Special Session 12: "Verification, Reliability, and Security Challenges in LLM-Enabled Vlsi Design and AI Hardware"

Room 2 (Cabernet)

Organizer: Shaahin Angizi (New Jersey Institute of Technology)
Chair: Ujjwal Guin (Auburn University)

Mitigating ReRAM Non-Idealities in In-Memory Computing Using Noise-Aware Training and Adaptive Experts for Large Language Models
Farshad Firouzi (Arizona State University)

Closing the Loop in LLM-Based Hardware Generation: An Autonomous Agentic Workflow for Robust Tpu Design
Shaahin Angizi (New Jersey Institute of Technology)

Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation
Hadi Kamali (University of Central Florida)

Towards LLM-Based Reasoning for Gate-Level Netlist Completion
Prithwish Basu Roy (New York University)

1:30 PM - 2:30 PM IP Session 7: "Hardware Security & Test"

Room 3 (Zinfandel)

Organizer: Jonti Talukdar (NVIDIA) & Sohrab Aftabjahani (Intel Corporation)
Chair: Jonti Talukdar (Arizona State University)

Addressing security for in-system test and SLM to enable in-field silicon monitoring
Lee Harrison (Siemens)

Scaling Hardware Security Assurance: AI-Driven Solutions Beyond Traditional Testing
Priyam Biswas (Intel)

Pre-Silicon Security Validation of Peripheral Roots of Trust using FPGA Emulation and Fuzzing
Sandhya Koteshwara (IBM Research)

2:30 PM - 3:30 PM Panel 3: Pre/Post-Silicon AI Applications for Test Cost, Quality, Yield Improvement and Time-to-Market

Room 1 (Merlot & Syrah)

Moderator: Yiorgos Makris (UCSD)

Abstract: The reach of Artificial Intelligence (particularly Data Analytics/Machine Learning and Generative AI) has extended to reducing test cost both in terms silicon area and test time/memory, helping rapidly converge on optimal parameters for Dft tools (for example for test point selection and ATPG), improving turnaround time for test program creation and validation, and improving yield by accelerating failure analysis and identifying systematic defect patterns. This panel of experts will examine the current state of the art of AI applications, and look into the crystal ball for untapped AI applications in the future.

Panelists:
Srikanth Venkatraman (Synopsys)
Sandeep Pendharkar (Qualcomm)
Abhijit Sathaye (Intel)
Shawn Blanton (CMU)
Senthil Singaravelu (Intel)

2:30 PM - 3:30 PM Special Session 13: "Security Vulnerabilities of Semiconductor Memories"

Room 2 (Cabernet)

Organizer: Biswajit Ray (Colorado State University)
Chair: Tong-Yu Hsieh (National Sun Yat-sen University)

Security Vulnerabilities in 3D Nand Flash Memory
Biswajit Ray (Colorado State University)

Are Emerging Memories Secure A Case Study on ReRAM
Biresh Kumar Joardar (University of Houston)

Tracing the Invisible: Unlocking Data from SRAM Aging Imprints
Ujjwal Guin (Auburn University)

2:30 PM - 3:30 PM Special Session 14: "Calibration techniques for Radio-Frequency systems"

Room 3 (Zinfandel)

Organizer: Arindam Sanyal (Arizona State University)
Chair: Ashok Mathur (AMD)

Non-Intrusive THz Chiplet Calibration Using Physics-Informed Neural Networks
Morteza Fayazi (University of Utah)

Trust Calibration for Rf and Mixed-Signal Systems: A Survey of Lightweight Hardware Security
Ankit Mittal (University of Connecticut)

Analog correlators with applications to low-power radar and spectrum sensing
Aravind Nagulu (Northeastern University)

3:30 PM - 3:45 PM Closing Session