Keynotes

📅 Monday, April 27, 2026 🕒 9:00 AM – 10:00 AM
Rafic Makki
Opening Keynote

Rafic Makki, Ph.D.

Head Technologist, Executive Director at Mubadala Capital Ventures
📍 Grand Ballroom
World Models – The Next Big Leap
Abstract

World models are emerging across applications ranging from humanoid robotics to healthcare and drug discovery. They represent a fundamental shift from next token prediction to next state prediction. This talk provides an overview of some of the most impactful innovations in this space and the implications on compute and hardware security.

Biography
Rafic oversees the science and technology strategy and roadmap for Mubadala Capital Ventures’ global investment fund with a portfolio of over 120 investments in technology startups in the US and Europe. He has served as Executive Fellow of Globalfoundries, developing strategies for technology differentiation across process nodes. He invented the iDDT pulse method for testing integrated circuits, published over 60 refereed papers. He co-designed and provided oversight for multi university R&D initiatives in AI, next generation computing, and Semi-Synbio, funded as a partnership between Mubadala and the Semiconductor Research Corporation. He currently serves as member of the Research and Economic Development advisory board of Georgia Tech and has served as member of the Board of Directors of the Semiconductor Research Corporation, member of the CTO committee of the Semiconductor Industry Association, and member of the National Decadal Planning Committee for Semiconductors. In academe, Rafic served as Professor at The University of North Carolina Charlotte, Dean of IT at UAE University and founding VP for Research at Masdar Institute of Science and Technology. In government, Rafic served as Head of Strategic Planning for the Abu Dhabi Education Council and senior advisor to the Director General. Rafic is an avid advocate for individuals with special needs and has served as a member of the Community and Legacy Committee of the Special Olympics 2019 World Summer Games.
📅 Tuesday, April 28, 2026 🕒 8:30 AM – 9:30 AM
Prithviraj Banerjee
Keynote 2

Prithviraj Banerjee

Senior Vice President of Innovation at Synopsys
📍 Grand Ballroom
Use of HPC, GPUs and AI/ML in ATPG and Fault Simulation
Abstract
Automatic Test Pattern Generation (ATPG) and Fault Simulation is used to screen for the presence or absence of physical defects or faults in a digital design. The process of ATPG and fault simulation involves a search through all possible input values and can take a very long time. This talk will start with a discussion of early work on using traditional high-performance computing (HPC) for ATPG and fault simulation pursued in academia and industrial research labs. We will then discuss how the latest HPC technologies of GPUs are being applied to speed up ATPG and Fault Simulation. Next, we will discuss how AI/ML is being applied to ATPG, fault simulation and Silicon Lifecycle Management. We will conclude the talk by looking at the future of agentic AI workflows with five levels of autonomy which we call “Reengineering Engineering.”
Biography
Prithviraj Banerjee is Senior Vice President of Innovation at Synopsys, and a member of the Executive Leadership team. Prior to that, he was CTO of Ansys, CTO of Schneider Electric, CTO of ABB, Managing Director at Accenture, and Director of HP Labs. Previously, he spent 20 years in academia as Professor, Chairman and Dean at the University of Illinois and Northwestern University. In addition, Prith has founded two EDA software companies, Accelchip and Binachip. He has served on the Board of Directors of Cray, CUBIC, and Turntide. He is a Fellow of the AAAS, ACM, IEEE, and the National Academy of Inventors. He received a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.
📅 Wednesday, April 29, 2026 🕒 8:30 AM – 9:30 AM
Debendra Das Sharma
Keynote 3

Dr. Debendra Das Sharma

Intel Senior Fellow and Chief I/O Architect of Data Center Group, Intel
📍 Grand Ballroom
Architecting the Chiplet Era: Solving Compute, Memory, and Communication Bottlenecks with UCIe®
Abstract
The computing landscape has adopted on-package integration of chiplets to meet the exponential performance demands of applications like AI and HPC. This transition is driven by three critical bottlenecks: the reticle limits of monolithic dies constraining compute scaling, the bandwidth bottleneck with off-package memory; and the power, bandwidth, and latency challenges with communication. Universal Chiplet Interconnect Express (UCIe®) provides the definitive open standard to solve these, enabling the seamless integration of heterogeneous compute, on-package memory, and communication chiplets. UCIe offers orders of magnitude improvement in bandwidth density, power efficiency, and latency over off-package interconnects with planar and vertical connectivity between chiplets. A unified Security, Manageability, and Debug and Test Architecture (UDA), leverages existing board and rack-level solutions for a seamless user experience. As an open standard, UCIe provides the foundation for power-efficient performance from silicon to the cloud for future computing platforms.
Biography
Dr. Debendra Das Sharma is an Intel Senior Fellow and Chief I/O Architect of Data Center Group, Intel. He is a member of NAE, an IEEE Fellow, and an AAIS Fellow. He has been leading PCI-Express®, CXL®, and UCIe® standards since their inception. He chairs CXL® and UCIe® consortia. He holds 230+ patents. He has received the IIT Kharagpur Distinguished Alumnus Award in 2019, the IEEE Region 6 Outstanding Award in 2021, the IEEE CAS Industry Pioneer Award in 2022, and the IEEE Computer Society McCluskey Award in 2024.