Early program

Kelson GENT, Akash AGRAWAL (Virginia Polytechnic Institute and State University), Michael HSIAO (Virginia Tech) A Framework for Fast Test Generation at the RTL
Shravan CHAGANTI (Iowa State University), Li XU (Texas Instruments), Degang CHEN (Iowa State University) A low-cost method for separation and accurate estimation of ADC noise, aperture jitter, and clock jitter
Dae-Hyun KIM, Linda MILOR (Georgia Institute of Technology) A Methodology of Estimating Memory Lifetime Using System-Level Accelerated Life Test and Error Correcting Codes
Claude THIBEAULT, Ali LOUATI (E. Tech. Sup. Montreal) A New Delay Testing Signal Scheme Robust to Power Distribution Network Impedance Variation
Ujjwal GUIN, Zhou ZIQI, Adit SINGH (Auburn University) A Novel Design-for-Security (DFS) Architecture to Prevent Unauthorized IC Overproduction
Dongrong ZHANG, Xiaoxiao WANG (Beihang University), Miao HE, Mark TEHRANIPOOR (University of Florida) A Novel Dynamic Obfuscation Scan Design for Protecting IPs against Scan-Based Attack
Pete SARSON (ams AG), shibuya SHOHEI, yanagida TOMONORI, Haruo KOBAYASHI (Gunma University) A Technique for Dynamic Range Improvement of Intermodulation Distortion Products for an Interpolating DAC-based Arbitrary Waveform Generator Using a Phase Switching Algorithm
Yan DUAN (IOWA STATE UNIVERSITY), Degang CHEN (Iowa State University) Accurate Jitter Decomposition in high speed link
Haralampos STRATIGOPOULOS (Sorbonne Universités, UPMC Univ. Paris 6, CNRS, LIP6), Christian STREITWIESER (ams AG) Adaptive test flow for mixed-signal ICs
Chang LIU (university of stuttgart), Michael KOCHTE, Hans-Joachim WUNDERLICH (University of Stuttgart) Aging Monitor Reuse for Small Delay Fault Testing
MD NAZMUL ISLAM, SANDIP KUNDU (University of Massachusetts Amherst) An Analytical Model for Predicting the Residual Life of an IC and Design of Residual-Life Meter
Wilson PRADEEP (Texas Instruments), Prakash NARAYANAN (Texas Instruments India Pvt. Ltd), Rubin PAREKJHI (Texas Instruments (India)) An Optimised SDD ATPG and SDQL Computation Method Across Different Pattern Sets
Guillaume RENAUD, Marc MARGALEF-ROVIRA, Manuel BARRAGAN, Salvador MIR (TIMA Laboratory) Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs
Xuan ZUO, Sandeep GUPTA (University of Southern California) Asymmetric sizing: an effective design approach for SRAM cells against BTI aging
Bonita BHASKARAN (NVIDIA Corp.), Sailendra CHADALAVADA, Shantanu SARANGI (Nvidia), Nithin VALENTINE (NVIDIA Corp.), Ayub ABDOLLAHIAN (Nvidia), Venkat Abilash Reddy NERALLAPALLY (NVIDIA Corp.) At-Speed Capture Global Noise Reduction & Low-Power Memory Test Architecture
Roya DIBAJ (Carleton University), Dhamin AL-KHALILI (Dept. of Elec. & Comp. Eng. Royal Military College), Maitham SHAMS (Dept. of Electronics, Carleton University), Saman ADHAM (TSMC Design Technology Canada Inc.) Comprehensive Investigation of Gate Oxide Short in FinFETs
Jan BURCHARD, Dominik ERB (University of Freiburg), Sudhakar REDDY (University of Iowa), Adit SINGH (Auburn University), Bernd BECKER (University of Freiburg) Efficient SAT-Based Generation of Hazard-Activated TSOF Tests
Irith POMERANZ (Purdue University) Fail Data Reduction for Diagnosis of Scan Chain Faults under Transparent-Scan
Kao-Chi LEE, Kai-Chiang WU, Chih-Ying TSAI, Mango CHAO (National Chiao Tung University) Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators
Deepak KRISHNANKUTTY (UMBC), Ryan ROBUCCI, Nilanjan BANERJEE (University of Maryland Baltimore County), Chintan PATEL (UMBC) FISCAL : Firmware Identification Using Side-Channel Power Analysis}
Yun CHENG (The Institute of Computing Technology of the Chinese Academy of Sciences), HUAWEI LI (Chinese Academy of Sciences), Ying WANG (The Institute of Computing Technology of the Chinese Academy of Sciences), Xiaowei LI (Institute of Computing Technology, CAS), Gao YINGKE, Bo LIU (Beijing Institute of Control Engineering) Flip-flop Clustering based Trace Signal Selection for Post-Silicon Debug
Aibin YAN (Anhui University), Zhengfeng HUANG, Maoxiang YI (Heifei University of Technology),  Jie Cui (School of Computer Science and Technology, Anhui University),  Huaguo Liang (School of Computer Science and Technology, Anhui University) HLDTL: High-performance, low-cost, and double node upset tolerant latch design
Yichuan LU, Georgios VOLANIS, Kiruba SUBRAMANI, Angelos ANTONOPOULOS, Yiorgos MAKRIS (UT Dallas) Knob Non-Idealities in Learning-Based Post-Production Tuning of Analog/RF ICs: Impact & Remedies
Sebastian SIATKOWSKI (University of California, Santa Barbara), Li-C. WANG (UC Santa Barbara), Nik SUMIKAWA, LeRoy WINEMBERG (NXP Semiconductors) Learning the Process of Correlation Analysis
Nour SAYED (KIT – Karlsruhe Institute of Technology), Fabian OBORIL, Rajendra BISHNOI (KIT), Mehdi TAHOORI (Karlsruhe Institute of Technology) Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM Cache
Yu-Hao HUANG, Ching-Ho LU, Tse-Wei WU, Yu-Teng NIEN (National Chiao Tung University), Ying-Yen CHEN, Max WU, Jih-Nung LEE (Realtek Semiconductor Corp.), Mango CHAO (National Chiao Tung University) Methodology of Generating Dual-Cell-Aware Tests
Md MOMTAZ, Suvadeep BANERJEE, Abhijit CHATTERJEE (Georgia Institute of Technology) On-Line Diagnosis and Compensation for Parametric Failures in Linear State Variable Circuits and Systems Using Time-Domain Checksum Observers
Athanasios CHATZIDIMITRIOU, Manolis KALIORAKIS, Sotiris TSELONIS, Dimitris GIZOPOULOS (University of Athens) Performance-Aware Reliability Assessment of Heterogeneous Chips
Ahmed IBRAHIM, Hans KERKHOFF (University of Twente) Structured Scan Patterns Retargeting for Dynamic Instruments Access
Zipeng LI (Duke University), Jon COLBURN (NVIDIA), Vinod PAGALONE (NVIDIA Corporation), Kaushik NARAYANUN (NVIDIA Corp.), Krishnendu CHAKRABARTY (Duke University) Test-Cost Optimization in a Scan-Compression Architecture Using Support-Vector Regression
Cheng XUE, Ronald BLANTON (Carnegie Mellon University) Test-Set Reordering for Improving Diagnosability
Irith POMERANZ (Purdue University) Using Piecewise-Functional Broadside Tests for Functional Broadside Test Compaction