IEEE VLSI Test Symposium 2016

April 25-27, 2016 Caesars Palace, Las Vegas, NV, USA

Main menu

Skip to primary content
  • Latest news
  • About the conference
  • The Symposium
  • Hotel reservation
  • Registration
  • Program
  • Tutorials

Post navigation

← Previous Next →

Key note presentation

Posted on March 22, 2016 by admin

Challenges and Opportunities in Electrical Characterization and Test for 14nm and Below

Andrzej J. STROJWAS (Chief Technologist, PDF Solutions, Inc. and Keithley Professor Carnegie Mellon University)

strojwas_andrzej

This entry was posted in Latest news by admin. Bookmark the permalink.
Proudly powered by WordPress