"The 3D & Chiplet TEST Workshop" focuses exclusively on test of and design-for-test for three-dimensional, chiplet-based, and stacked ICs, including systems-in-package (SiP), package-on-package (PoP), 3D-Stacks based on through-silicon vias (TSVs), micro-bumps, and/or interposers.

While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing and repairing such products.

The 3D & Chiplet TEST Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.

Submission: Submissions must be sent as PDF files. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results.

Review: 3D & Chiplet TEST focuses on early information sharing and free discussions; therefore, the workshop will not publish formal proceedings. Instead, the workshop will make available to all its registered participants an electronic workshop digest, which includes all material that authors/presenters are willing to contribute in PDF format: abstract, paper, slides, posters, background material, etc. This will allow authors to be free in their choice to submit their workshop paper later to a formal (IEEE or otherwise) journal, leveraging the audience feedback and discussions on the paper presentation at the 3D & Chiplet TEST Workshop.

Presentation: an author of each publication must attend the workshop in person for a presentation showcasing its influence and impact.

Submit now!

Submission deadline: September 27, 2024
Notification: October 9, 2024
Camera-ready material: October 28, 2024

"3D & Chiplet TEST” will take place in conjunction with the 2024 IEEE International Test Conference (ITC) and is sponsored by the IEEE Philadelphia Section in concurrence with the Test Technology Technical Council (TTTC) of IEEE Computer Society.