Call for submissions
Download the Call for Submissions
Topic Areas – You are invited to participate and submit your contributions to the 3D & Chiplet TEST Workshop. The workshop’s areas of interest include (but are not limited to) the following topics:
- Defects due to Wafer Thinning
- DfT Architectures for 3D-ICs
- D2D PHY monitoring, test & repair
- EDA Design-to-Test Flow for 3D-SICs
- Lane Fault Models & Failure Analysis
- Fault-Tolerant Design for multi-die
- Handling and Testing Singulated ICs
- HBM Base-die & stack test & repair
- Interposer Testing & Debugging
- Known-Good Die / Known-Good Stack
- Monitor interconnect signal integrity
- Pre-, Mid-, and Post-Bond Testing
- RAS for 2.5D and 3D ICs
- Stacking Yield, Redundancy & Repair
- Standards for 3D Test & Repair, IEEE P3405, IEEE 1838
- Standards for test description 3dBlox
- Test Cost Modelling for 3D Packages
- Test Flow Optimization for 3D Packages
- Tester Architecture incl. ATE and BIST
- TSV-based lane test & repair
- UCie-based Multi-Die Test & Debug
- Wafer Probing and Probe Marks of 3D-SICs