Abstract: The development of noisy, intermediate-scale quantum computers has raised the possibility of addressing problems that are intractable with classical computation, even in the absence of quantum error correction. In this talk, I shall present a brief overview of superconducting quantum technology at IBM, and discuss metrics to benchmark the performance of NISQ processors. I shall then discuss our experimental implementations of hybrid quantum-classical algorithms on these systems, and demonstrate that the accuracy of these computations is largely limited by decoherence. I shall then introduce an error mitigation technique to obtain zero-noise estimates of expectation values, that requires no additional quantum resources, and is therefore readily accessible to NISQ hardware. These techniques have great applicability to a range of computations, extending the computational reach of noisy quantum processors.

 Abstract: The advanced technology that drives the next generation of vehicles will be presented. Building up from Newtonian physics and electrical engineering we will analyze motor efficiency, reliability, safety, performance and manufacturing cost. By comparing that to gasoline-powered cars we can present a unique science-based foundation for a sound economical and environmental transportation policy. For a fact-based bigger picture we will derive the full well-to-wheel cost  emissions and other impacts of all propulsion options. We will show that the results are much more nuanced than the polarized information from either side of the political debate on climate change.

 Abstract: Continuing a tradition at the IEEE VLSI Test Symposium this new topic session presents two interesting talks on new emerging computing and testing techniques. The first talk focuses on carbon nanotube electronics while the second talk discusses about wafer level testing under magnetic field.

 Abstract: Safety is one of the crucial features of autonomous drive platforms, and semiconductor chips used in these architectures must guarantee functional safety aspects mandated by ISO 26262 standard. This special session discusses the in-system-test (IST) architecture and solutions that helps with achieving highest functional safety levels on the NVIDIA Drive-AGX platforms.

 Abstract: The continuing decrease in feature size of integrated circuits, and the increase of the complexity and cost of design and
fabrication has led to outsourcing the design and fabrication of integrated circuits to third parties across the globe, and in turn
has introduced several security vulnerabilities. This special session discusses these security threats in the supply chain and the state-of-the-art countermeasures to tackle such threats.

 Abstract: Over the last decade there has been a surge of activity in employing advanced statistical analysis and machine learning methods to various test-related tasks. The topic is no longer simply a matter of academic curiosity but, rather, a pressing need of the industry as it seeks to address various challenges. In this session, three industry experts have been invited to give their perspective, describe machine learning use cases, and discuss challenges and future work ideas. The three talks will cover the use of deep learning for hotspot detection, the challenge of rendering machine learning-based decisions in the semiconductor industry trustable and explainable, and data analytics across the complete product cycle towards improved product reliability.

 Abstract: Artificial Intelligence (AI) is becoming an integral part of our daily lives. AI is also becoming a major component for test community, cyber-security community, manufacturing, Internet-of-Things, and more. AI may be able to analyze test data, yield analysis, penetration test, fuzzy test, and negative test to extract vulnerabilities and defects. However, there may be a limited control on what AI systems learn and policies they internalize in their learning process. AI learns a task through objective functions. Defining objective functions to reflect security concerns and verification is of high importance. If objective function does not cover all aspects of security requirements and the correct functionality, there is a chance that AI learns vastly different concepts and ends up in unwanted situations. Further, AI may internalize some sensitive information which is decodable by reverse engineering. The panelists will address a number of issues in this emerging and inter-disciplinary field.

 Abstract: This Embedded Tutorial is dedicated to the recent advances related to the analysis and optimization of fault-tolerance characteristic of hardware-implemented Spiking Neural Networks, with special emphasis on circuits designed using nonvolatile emerging memory technologies.

 Abstract: The IEEE 1687-2014 standard introduced the concept of portable, retargetable tests for digital circuits and taught how to apply them via a JTAG Test Access Port. Two follow-on standardization efforts address the topics of portable, retargetable analog tests (IEEE P1687.2) and applying analog or digital tests via non-TAP interfaces (IEEE P1687.1). IEEE P2427 complements these efforts by defining how to measure and report coverage of analog tests. This IP session will use a running example to show how all three initiatives play together.

 Abstract:

 Abstract: There is a growing demand for low-cost and effective test solutions to support state-of-the-art analog and mixed-signal systems that are continuously increasing in complexity and functionality, while decreasing in product cost. This innovative practice session highlights various aspects of design for test (DfT) in high-complexity, analog-dominated systems with three talks that focus on: DfT in power management integrated circuits (ICs), an alternative testing method to analog test bus, and pre-silicon built-in self-test (BIST) verification, where BIST is used to monitor complex mixed-signal systems. These talks will be given by industry experts from Dialog Semiconductor, Xilinx, and Texas Instruments.

 Abstract: Silicon photonics is a field of growing importance as the need for communication speed and bandwidth continues to increase dramatically. This special session will provide background on Silicon Photonics and the impact of silicon photonics on test through two talks by experts in the field.

 Abstract: Hardware acceleration for Artificial Intelligence (AI) is now a very competitive and rapidly evolving market. As a result, fast time-to-market is a leading concern for this segment. To speed up time-to-market and ensure quality, new design-for-test (DFT) architectures, new DFT methodologies and technologies are emerging. AI chips are typically very big with many identical and non- identical cores, distributed memories, high-speed IOs, which makes testing of such a gigantic SoC a very challenging task. We found it is very important for us to understand these new challenges from the point of views of DFT engineers. In this innovative practice session, we invited three DFT experts from three AI chip companies to share their experiences of DFT on AI chips.

 Abstract: Many important application domains, including machine learning, feature intrinsically noise tolerant algorithms. While this may translate into relaxed constraints for testing and verification of approximate systems, distinguishing actual design bugs from what is being approximated also becomes harder. In this special session, using representative case studies, we pose several challenges for the test and verification community as approximate computing becomes more prevalent as a design of choice.

 Abstract: This innovative practice session includes three presentations which discuss test and reliability issues and solutions for external and embedded memories. At speed test for external memories, memory array diagnosis and interconnect faults detection, as well as the peculiarities of supporting different memory IPs including DRAM and HBM2 are among the topics discussed. As for embedded memories, FIT rate calculation and mitigation methodology is presented which is shown to be critical for automotive SoCs.

 Abstract: The term CyberSecurity means many different things to many people — some think of data security, some think of identity protection, some think of intrusion attacks on the internet or USB ports. In reality, CyberSecurity represents any type of attack on computing machines and one of the attacks that is often overlooked is attacks by the supply chain to inject malfeasant circuitry into semiconductor devices as they are made. This is the one aspect of Design-for-Security and Design-for-Trust that is often overlooked. This IP session will propose three talks on CyberSecurity from both industry and academia.

 Abstract: The IP session highlights three innovative test practices in Japan, which include DC parametric test time reduction using digital controlled DC resource and deep reconsideration for ADC distortion testing as well as test time reduction of low sampling rate and high resolution ADC linearity. These would be useful for automotive and IoT application device testing.

 Abstract: Functional safety has emerged as the number one consideration when designing solutions for automotive industry. Automotive embedded design is witnessing exponential increase in complexity and product variety. This is primarily driven by the personalized products and high-tech solutions for safety and comfort demanded by the customers, regulators and stringent standards put in place. This panel will discuss the implications of automotive functional safety requirements on all aspects of the SOC design, manufacturing quality and particularly in-system functional safety with respect to the role of design-for test (DFT), functional verification and emulation. The panel will further discuss the range solutions for different categories of automotive SOCs.

 Abstract: In this IP session, there will be 2 presentations focusing on how to increase the in-field quality level of A/MS devices. The 1st presentation will discuss how to increase the observed return rates of Automotive ICs to 10ppb but at the same time as removing the costly burn in stage.
The 2nd presentation goes into detail of how to use a System Level Test to increase the reliability of an Automotive device, by adding a functional test to the flow of the test program.

 Abstract: This embedded tutorial presents a brief survey of digital delay fault testing, which lists 100+ references on fault models, simulators, ATPG, DFT, and tools. Continuing studies are needed in this maturing field for new technologies, signal integrity, process variations, faster than critical path operation, asynchronous circuits, counterfeit ICs, and hardware Trojans. This information is compiled to provide direction to students, practicing engineers, and researchers alike.

 Abstract: Achieving quicker product yield ramp depends on how quickly manufacturing defects and their underlying root causes are identified, specifically the systematic ones. The IP session discusses the concepts, challenges, and opportunities of semiconductor yields and industry-proven methodologies that improve yield of digital semiconductor products using machine learning based analysis of volume scan test diagnosis results. We also discuss what it takes to set-up and perform successful hardware based non-destructive fault isolation on wafer and packaged (modules) parts. The packed modules add a layer of complexity with respect to cooling and backside sample preparation.