IEEE VLSI Test Symposium 2015

VTS registration page is NOW OPEN!

Don’t miss VTS advanced registration rate. Register by April 10th, 2015.

Register now!!

The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, debug and repair of microelectronic circuits and systems.

The VTS Program Committee invites original, unpublished paper submissions for VTS 2015Paper submissions should be complete manuscripts, up to six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: author name(s) and affiliation(s), and the mailing address, phone number, and e-mail address of the contact author. A 50-word abstract and five keywords identifying the topic area are also required.

C. THIBEAULT – General Chair
Ecole de Technologie Superieure (Canada)
L. ANGHEL – Program Chair
University of Grenoble-Alpes, TIMA Laboratory (FR)


  • 2.5D, 3D and SiP Test
  • Analog, Mixed-Signal & RF Test
  • ATE Architecture & Software
  • ATPG & Compression
  • Built-In Self-Test (BIST)
  • Defect & Current Based Test
  • Defect and Fault Modeling, Defect based Fault Analysis
  • Delay & Performance Test
  • Dependability and Reliability
  • Design For Testability
  • Design Verification/Validation
  • Diagnosis and Debug
  • Embedded System & Board Test
  • Embedded Test Methods
  • Emerging Technologies Test
  • FPGA Test
  • Hardware Security
  • High Level System Testing
  • Memory Test and Repair
  • On-Line Test & Error Correction
  • Power and Thermal Issues in Test
  • System-on-Chip (SOC) Test
  • Test Economics/Test Quality
  • Test of Biomedical Devices
  • Test of High-Speed I/O
  • Test of MEMS
  • Test Resource Partitioning
  • Test Standards
  • Transients and Soft Errors