Program

MONDAY, APR. 27th 2015

07:30-08:30 Registration

08:30-10:30 Plenary Session
Room: Vintner’s Court

  • Welcome Message
    C. Thibeault (E. Tech. Sup. Montreal), General Chair
  • Program Introduction
    L. Anghel (University of Grenoble Alpes, TIMA Laboratory), Program Chair
  • Opening Keynote: The Future of Test: Bold, Not So Bold and Humorous Predictions from The Crystal Ball
    Kenneth Wagner, Vice President of Engineering, Communication Products Division, PMC-Sierra (Biography)
    CRW_8680.sizedConferences, symposia and workshops focus us on the latest test results and next generation of innovative techniques in ATPG, DFT and BIST for advanced process technologies. In this keynote talk, let’s take a step back and contemplate the bigger picture as we step forward in time. What could test look like in five years, ten years and more? Do we still use scan? Did we finally discard the stuck-at fault model? Will we be industry-specific? What do new process and packaging technologies mean to us? Will acceptable Defect Levels fall to zero? Will we be paid for RMA performance? Futurists and science fiction writers are often the only adventurers among us. But thanks to the crystal ball, your friendly soothsayer will stride fearlessly into the future. Come experience test as it might or may or could or will be. Be impressed! And prepare for your roles to change from hardware test gurus to system impresarios.Then, if you will be so kind as to join me here again in the Year 2025, let’s review the prognostications and do it all over again!
  • Invited Talk: New Opportunities in the Internet of Things
    Yankin Tanuhan, Vice President Engineering, Synopsys (Biography)
  • Awards Presentation
    Y. Zorian (Synopsys), Ex-Officio

10:30-11:10 BREAK

11:10-12:10 Session 1A: Emerging Technologies Testing
Room: Hans Kornell
Moderator: Michel Renovell (LIRMM, France)

  • Fault Diagnosis for Flow-Based Microfluidic Biochips
    Kai HU (Duke University, USA), Bhargab BHATTACHARYA (Indian Statistical Institute – India), Krishnendu CHAKRABARTY (Duke University, USA) (Best Paper Award Candidate)
  • Rapid Online Fault Recovery for Cyber-physical Digital Microfluidic Biochips
    Christopher JARESS (University of California, Riverside, USA), Daniel GRISSOM (Azusa Pacific University, USA), Philip BRISK (University of California, Riverside, USA)
  • Fault Modeling and Testing of 1T1R Memristor Memories
    JIN-FU LI (National Central University – Taiwan), Yong-Xiao CHEN (National Central University – Taiwan)

11:10-12:10 Session 1B: Analog, Mixed and RF Testing I
Room: Freemark Abbey
Moderator: Victor Champac (INAOE, Mexico)

  • A Low Cost Jitter Separation and Characterization Method
    Li XU (Iowa state university, USA), Degang CHEN (Iowa State University, USA)
  • Ultrafast Stimulus Error Removal Algorithm for ADC Linearity Test
    Tao CHEN (Iowa State University, USA), Degang CHEN (Iowa State University, USA)
  • Disturbance-free BIST for Loop Characterization of DC-DC Buck Converters
    Navankur BEOHAR (Arizona State University , USA), Priyanka BAKLIWAL (Arizona State University, USA), Sidhanto ROY (Arizona State University, USA), Debashis MANDAL (Arizona State University, USA), Bertan BAKKALOGLU (Arizona State University, USA), Sule OZEV (Arizona State University, USA)  (Best Paper Award Candidate)

11:10-12:10 IP Session 1C: New Technologies, New Challenges – 1
Room: Buena Vista/ Sutter Home
Organizer: TM Mak (Globalfoundries, USA)
Moderator: Paul Tracey (Altera, USA)

  • Designing with FinFETs
    Witek Maszara (Globalfoundries, USA)
  • Test Implications of FinFETs
    Greg Yeric (ARM, USA)
  • Design, Test & Repair Methodology for FinFET-based Memories
    Yervant Zorian (Synopsys, USA)

12:10-13:40 LUNCH BREAK

13:40-14:40 Session 2A: Dependability and Reliability
Room: Hans Kornell
Moderator: Valentin Gherman (CEA-LIST, France)

  • A Multi-Layered Methodology for Defect-Tolerance of Datapath Modules in Processors
    Hsunwei HSIUNG (University of Southern California, USA), Sandeep GUPTA (University of Southern California, USA)
  • PPB: Partially-working Processors Binning for Maximizing Wafer Utilization da
    CHENG (USC, USA), Sandeep GUPTA (University of Southern California, USA) BPA
  • Detailed Soft Error Vulnerability Analysis using Synthetic Benchmarks
    Shahrzad MIRKHANI (University of Texas at Austin, USA), Balavinayagam SAMYNATHAN (University of Texas at Austin, USA), Jacob ABRAHAM (University of Texas at Austin, USA) (Best Paper Award Candidate)

13:40-14:40 Session 2B: Embedded Tutorial – VLSI Security and Test
Room: Freemark Abbey
Organizer: Ozgur Synanoglu (NYU, USA)
Moderator: Jeyavijayan Rajendran (NYU, USA)

  • Test Infrastructure Misuse for Cipher Chips
    Sk Subidh Ali, Ozgur Sinanoglu and Ramesh Karri (New York University)
  • A Call to Action: Securing IEEE 1687 and the Need for an IEEE Test Security Standard
    Jennifer Dworak, Al Crouch (Southern Methodist University & ASSET InterTech)
  • Enabling Unauthorized RF Transmission below Noise Floor with no Detectable Impact on Primary Communication Performance
    Doohwang Chang, Bertan Bakkaloglu, Sule Ozev (Arizona State University)

13:40-14:40 IP Session 2C: New Technologies, New Challenges – 2
Room: Buena Vista/ Sutter Home
Organizer: TM Mak (Globalfoundries, USA)
Moderator: Suraj Sindia (Intel, USA)

  • Test Challenges for Complex 2.5D SOC Designs
    Jon Colburn (NVIDIA, USA)
  • 3D IC design and test challenges: System architect perspective
    Sandeep Goel (TSMC, USA)
  • Yield challenges in stacked silicon interconnects technology and methods to achieve high yields
    Raghu Chaware (Xilinx, USA)

14:40-15:10 BREAK

15:10-16:10 Session 3A: Processor, System Testing and Yield
Room: Hans Kornell
Moderator: Ismed Hartanto (Xilinx, USA)

  • Extracting Effective Functional Tests from Commercial Programs
    Sreekumar KODAKARA (Intel Corp., USA), Mehul SAGAR (Intel Corp., USA), Joel YUEN (Intel Corp., USA)
  • Statistical Techniques for Predicting System-Level Failure using Stress-Test Data
    Harry CHEN (MediaTek Inc. – Taiwan), Shih-Hua KUO (National Chiao Tung University – Taiwan), Jonathan TUNG (MediaTek Inc. – Taiwan), Mango CHAO (National Chiao Tung University – Taiwan) BPA
  • Yield Prognosis for Fab-to-Fab Product Migration
    Ali AHMADI (UT Dallas, USA), Ke HUANG (San Diego State University, USA), Nahar AMIT (Texas Instruments, USA), Orr BOB (Texas Instruments, USA), Pas MICHAEL (Texas Instruments, USA), John CARULLI (GlobalFoundries, USA), Yiorgos MAKRIS (UT Dallas, USA) (Best Paper Award Candidate)

15:10-16:10 Special Session 3B: New Topic: 3D Integration of Nanoelectronic Devices Above CMOS
Room: Freemark Abbey
Organizer and Moderator: Bozena Kaminska (U. Simon Fraser, Canada)

  • 3D Integration of Nanoelectronic Devices Above CMOS
    Dominique Drouin, 3IT Université de Sherbrooke, Canada

15:10-16:10 IP Session 3C: Debug & Diagnosis
Room: Buena Vista/ Sutter Home
Organizer: Mike Ricchetti (Synopsys, USA)
Moderator: Mike Ricchetti (Synopsys, USA)

  • P1149.10 High Speed JTAG – debug using a fire hose rather than a straw
    CJ Clark (Intellitech, USA)
  • The New Era of EDA Supported Post-Silicon Validation
    Eric Rentschler (Mentor Graphics, USA)
  • FPGA as Programmable Diagnosis Platform
    Eric Thorne and Jenny Fan (Xilinx, USA)

16:10-16:30 BREAK

16:30-18:00 Panel Session 4A: When will the cost of dependability end innovation in computer design?
Room: Hans Kornell
Organizer: Valeria Bertacco (U. Michigan, USA)
Moderator: Tim Cheng (University of California at Santa Barbara, USA)

Panelists:

  • Andrew Kahng (University of California at San Diego)
  • Ritesh Parikh – Power and Performance Architect (PDG Architecture Group, Intel Corp).
  • Siva Kumar Sastri Hari – Research Scientist (Architecture Research Group, NVIDIA)
  • Todd Austin – Professor (University of Michigan)
  • TM Mak (Globalfoundries, USA)

16:30-18:00 Session 4B Hot Topic: Statistical Test Methods
Room: Freemark Abbey
Organizers and Moderators: Manuel Barragan (TIMA Laboratory, France) and Gildas Leger (IMSE CNM, Spain)

  • Statistical techniques and metrics for alternate testing of analog/RF integrated circuits?
    Florence Azais (LIRMM, France)
  • Targeting Opens versus TDF in Two-Pattern Scan Testing: What Defect Statistics May Be Telling Us
    Adith Singh (Auburn University, USA)
  • Random sampling for fault simulation: intuition vs. theory and reality
    Stephen Sunter (Mentor Graphics, Canada)
  • What Gold can be Mined from Test Data?
    Shawn Blanton (Carnegie Mellon University, USA)

 

TUESDAY, APR. 28th 2015

07:30-08:30 Registration and Breakfast

08:30-09:30 Session 5A: 3D IC TEST
Room: Hans Kornell
Moderator: Charutosh Dixit (Avago, USA)

  • ExTest Scheduling for 2.5D System-on-Chip Integrated Circuits
    Ran WANG (Duke University, USA), Guoliang LI (Advanced Micro Devices – China), Rui LI (Advanced Micro Devices – China), Jun QIAN (Advanced Micro Devices – China), Krishnendu CHAKRABARTY (Duke University, USA)
  • Pulse Shrinkage Based Pre-bond Through Silicon Vias Test in 3D-IC
     Hao CHANG (Hefei University of Technology – China), Huaguo LIANG (Heifei University of Technology – China)
  • Testing of 3D-Stacked ICs With Hard- and Soft-Dies – A Particle Swarm Optimization Based Approach
    RAJIT KARMAKAR (INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR – India), ADITYA AGARWAL (INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR – India), Santanu CHATTOPADHYAY (IIT Kharagpur – India)

08:30-09:30 Session 5B: Diagnosis and Debug
Room: Freemark Abbey
Moderator: Vivek Chickermane (Mentor Graphics, USA)

  • Improving Diagnosis Resolution of a Fault Detection Test Set
    Andreas RIEFERT (University of Freiburg – Germany), Matthias SAUER (University of Freiburg – Germany), Bernd BECKER (University of Freiburg – Germany), Sudhakar REDDY (University of Iowa, USA) 
  • Improving the Accuracy of Defect Diagnosis by Considering Reduced Diagnostic Information
    Irith POMERANZ (Purdue University, USA) 
  • Signature Oriented Model Pruning to Facilitate Multi-Threaded Processors Debugging
    Fatemeh REFAN (University of Tehran – Iran, Islamic Republic of), Bijan ALIZADEH (University of Tehran – Iran, Islamic Republic of), Zainalabedin NAVABI (University of Tehran – Iran, Islamic Republic of) 

08:30-09:30 IP Session 5C:  Advancements in Test – Keeping Moore Moving!
Room: Buena Vista/ Sutter Home
Organizer: Enamul Amyeen (Intel, USA)
Moderator: Enamul Amyeen (Intel, USA)

  • Challenges with manufacturing huge chips –an interplay between test and debug
    John Bowling (Intel, USA)
  • Technology and the pursuit of Moore’s Law
    Greg Yeric (ARM, USA)
  • Test Technology at a standstill with “More than Moore”
    T.M. Mak (Globalfoundries, USA)

09:30-09:50 BREAK

09:50-10:50 Session 6A: Analog, Mixed and RF Testing II
Room: Hans Kornell
Moderator: Paul Berndt, Cypress, USA

  • At-Product-Test Dedicated Adaptive Supply-Resonance Suppression   
    Kohki TANIGUCHI (Kobe University – Japan), Noriyuki MIURA (Kobe University – Japan), Taisuke HAYASHI (Kobe University – Japan), Makoto NAGATA (Kobe University – Japan)  (Best Paper Award Candidate)  
  • UWB Direct Pseudo Random Noise Synthesis for Adaptive RF System Testing 
    Xian WANG (georgia institute of technology, USA), Debashis BANERJEE (Georgia Institute of Technology, USA), Abhijit CHATTERJEE (Georgia Institute of Technology, USA)      
  • Automated Testing of Mixed-Signal Integrated Circuits by Topology Modification
    Anthony COYETTE (KULeuven – Belgium), Georges GIELEN (KU Leuven – Belgium), Esen BARIS (KU Leuven – Belgium), Wim DOBBELAERE (ON Semiconductor – Belgium), Ronny VANHOOREN (ON Semiconductor – Belgium)

09:50-10:50 Session 6B Hot Topic : Memory Test and Repair Techniques for Deep Nanometric Technologies
Room: Freemark Abbey
Organizer: Yervant Zorian (Synopsys, USA)
Moderator: Harry-H Chen (Mediatek, Taiwan)

  • Impact of Parameter Variations on FinFET Faults
    G. Harutyunyan, G. Tshagharyan, Y. Zorian (Synopsys, USA)
  • Memory Repair for High Defect Densities
    M. Nicolaidis and P. Papavramidou (TIMA Laboratory, France)

09:50-10:50 IP Session 6C: Innovations in DFx Use and Reuse
Room: Buena Vista/ Sutter Home
Organizers: TM Mak (Globalfoundries USA)
Moderator: Onnik Yaglioglu (FormFactor, USA)

  • Targeting Timing Faults at the Board Level: High Performance Test Instrumentation and Relevant Fault Models
    Artur Jutman  (Testonica, USA)
  • Selective Save Restore Using Scan Grouping and Dynamic Clock Control
    Sanjay Kumar (Broadcom, USA)
  • Challenges and Opportunities Testing Programmable Logic
    Paul Tracy (Altera, USA)

10:50-11:10 BREAK

11:10-12:10 Session 7A: New Direction In Testing
Room: Hans Kornell
Moderator: Peter Maxwell (ON Semiconductor, USA)

  • Horizontal-FPN fault coverage improvement in production test of CMOS imagers
    Richun FEI (STMicroelectronics – France), Salvador MIR (TIMA Laboratory – France), Jocelyn MOREAU (STMicroelectronics – France) 
  • Capacitive Coupling Mitigation for TSV-based 3D ICs
    Ashkan EGHBAL (University of California Irvine, USA), Pooria M.YAGHINI (University of California Irvine, USA), Nader BAGHERZADEH (University of California Irvine, USA) 
  • Improving Real-time Accuracy for On-chip Diagnosis via Incremental Learning
    Xuanle REN (Carnegie Mellon University, USA), Mitchell MARTIN (Carnegie Mellon University, USA, Vitor TAVARES (University of Porto – Portugal), Shawn BLANTON (Carnegie Mellon University, USA)

11:10-12:10 Special Session 7B: Embedded Tutorial/Hot Topic: Resiliency Challenges in sub-100 Technologies
Room: Freemark Abbey
Organizer and Moderator: Mehdi Tahoori (Karlsruhe Institute of Technology, Germany)

  • The challenges and meta-challenges of resiliency
    Rob Aitken, (ARM, USA)
  • Realizing the Future of Aerospace through Resilient IC Design
    Ethan Cannon (Boeing)
  • Resiliency – the tough road ahead
    Mandy Pant (Intel, USA)

11:10-12:10 IP Session 7C: Mixed Signal Test and Debug
Room: Buena Vista/ Sutter Home
Organizer: Suriyaprakash Natarajan (Intel, USA)
Moderator: Suriyaprakash Natarajan (Intel, USA)

  • What’s more important for high-speed IO? Test or Debug?
    Srinivas Modekurty (Intel, USA)
  • MIPI D-PHY RX+, Optimized Test Configuration
    Ashraf Takla (Mixel, USA)
  • Application of On-Chip, C based post analysis to the test of Mixed Signal IPs
    Shahin Toutounchi (Speaker), Andrew Taylor, Seng Lao and Ekarat Laohavaleeso (Xilinx, USA)

12:10-13:30 LUNCH BREAK

13:30-15:00 Special Session 8A: Panel Analog/RF BIST: Are we there yet?
Room: Hans Kornell
Organizer: Sule Ozev (ASU, USA)
Moderator: Linda Milor (Georgia Tech, USA)

Participants:

  • Abhijit Chatterjee (Georgia Tech, USA)
  • Haralampos Stratigopoulos (TIMA Laboratory, France)
  • Steve Sunter (Mentor Graphics, USA)
  • Tao Liu (Qualcomm, Inc, USA)

13:30-15:00 Special Session 8B: Panel The root cause of No Fault Found is…
Room: Freemark Abbey
Organizer: Erik Larsson (Lund University, SE)
Moderator: B. Eklow (Cisco, USA)

Participants:

  • Scott Davidson (Oracle, USA)
  • Christoph Lotz (Aster Technologies, USA)
  • Rob Aitken (ARM, USA)
  • Artur Jutman (Testonica Lab, USA)

13:30-15:00 Special Session 8C: E.J. McCluskey Doctoral Thesis Competition (Presentations & Posters)
Room: Buena Vista/ Sutter Home
Organizer: Ke Huang (San Diego State University, USA)

Contestants:

  • Abhishek Basak
    Advisor: Swarup Bhunia, Case Western Reserve University
  • Navankur Beohar
    Advisor: Bertan Bakkaloglu, Arizona State University
  • Sergej Deutsch
    Advisor: Krishnendu Chakrabarty, Duke University
  • Ashkan Eghbal
    Advisor: Nader Bagherzadeh, University of California, Irvine
  • Bahar Farahani
    Advisor: Saeed Safari, University of Tehran
  • Amirali Ghofrani
    Advisor: Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
  • Shahrzad Mirkhani
    Advisor: Jacob A. Abraham, University of Texas at Austin
  • Lu Wang
    Advisor: Bao Liu, The University of Texas at San Antonio
  • Li Xu
    Advisor: Degang Chen, Iowa State University
  • Fangming Ye
    Advisor: Krishnendu Chakrabarty, Duke University

15:30-22:00 SOCIAL PROGRAM

WEDNESDAY, APR. 29th 2015

07:30-08:30 Registration and Breakfast

08:30-09:30 Session 9A: Design Verification and Validation
Room: Hans Kornell
Moderator: Chen-Huan Chiang (Alcatel Lucent, USA)

  • Abstraction-based Relation Mining for Functional Test Generation
    Kelson GENT (Virginia Polytechnic Institute and State University, USA), Michael HSIAO (Virginia Tech, USA)
  • Random Pattern Generation for Post-Silicon Validation of DDR3 SDRAM
    Max YANG (National Chiao Tung University – Taiwan), Shih-Hua KUO (National Chiao Tung University – Taiwan), Tzu-Hsuan HUANG (National Chiao Tung University – Taiwan), Chi-Hung CHEN (Winbond Electronics Corporation – Taiwan), Chris LIN (Winbond Electronics Corporation – Taiwan), Mango CHAO (National Chiao Tung University – Taiwan)
  • UPF-based Formal Verification of Low Power Techniques in Modern Processors
    Reza SHARAFINEJAD (University of Tehran – Iran, Islamic Republic of), Bijan ALIZADEH (University of Tehran – Iran, Islamic Republic of), Masahiro FUJITA (Univ. of Tokyo – Japan)

08:30-09:30 Session 9B: Aging induced Reliability Issues
Room: Freemark Abbey
Moderator: Bernd Becker (U Freibourg, DE)

  • MBIST and Statistical Hypothesis Test for Time Dependent Dielectric Breakdowns due to GOBD vs. BTDDB in an SRAM Array
    Woongrae KIM (Georgia Institute of Technology, USA), Linda MILOR (Georgia Institute of Technology, USA)
  • An Early Design Methodology to Select Critical Paths under Surveillance to Keep Safe Circuit Operation due to NBTI Aging
    Andres GOMEZ CHACON (INAOE – Mexico), Victor CHAMPAC (INAOE – Mexico), Leticia BOLZANI POEHLS (Catholic University of Rio Grande do Sul (PUCRS) – Brazil), Fabian VARGAS (Catholic University – PUCRS – Brazil)
  • Integral Impact of BTI and Voltage Temperature variation on SRAM Sense Amplifier
    Innocent AGBO (TU Delft – Netherlands), Mottaqiallah TAOUIL (Delft University of Technology – Netherlands), Said HAMDIOUI (Delft University of Technology – Netherlands), Halil KUKNER (Imec Belgium – Belgium), Pieter WECKX (Imec Belgium – Belgium), Praveen RAGHAVAN (Imec Belgium – Belgium), Francky CATTHOOR (Imec Belgium – Belgium)

08:30-09:30 IP Session 9C: HW Security
Room: Buena Vista/ Sutter Home
Organizer and Moderator: An Chen (Globalfoundries, USA)

  • Aging monitoring technique for counterfeit IC detection
    Peilin Song (Speaker) & Franco Stellari (IBM, USA)
  • www.IoST: The What, Why and When of Internet of Secure Things
    Rob Aitken (ARM, USA)
  • Secured Silicon: securing the silicon manufacturing
    Michael Chen (Mentor Graphics, USA)

09:30-09:50 BREAK

09:50-10:50 Session 10A: Delay, Power and Security
Room: Hans Kornell
Moderator: Yiorgos Makris (U.T. Dallas, USA)

  • A Robust Digital Sensor IP and Sensor Insertion Flow for In-Situ Path Timing Slack Monitoring in SoCs
    Mehdi SADI (University of Connecticut, USA), Mohammad TEHRANIPOOR (University of Connecticut, USA)
  • Scalability Study of PSANDE: Power Supply Analysis for Noise and Delay Estimation
    Sushmita KADIYALA RAO (UMBC, USA), Bharath SHIVASHANKAR (University of Maryland Baltimore County, USA), Ryan ROBUCCI (University of Maryland Baltimore County, USA), Nilanjan BANERJEE (University of Maryland Baltimore County, USA), Chintan PATEL (UMBC, USA)
  • Trace Impedance based Authetication: A method towards Robust Counterfeit Printed Circuit Board (PCB) Detection
    Andrew HENNESSY (Case Western Reserve University, USA), Swarup BHUNIA (Case Western Reserve University, USA), Fengchao ZHANG (Case Western Reserve University, USA)

09:50-10:50 Session 10B Hot Topic: Field and Experimental Data on Soft Error in Large-Scale HPC Systems and Analysis of the Implication for Exascale System Design
Room: Freemark Abbey
Organizer: Paolo Rech (UFRGS, Brazil)
Moderator: Subhasish Mitra (U Standford, USA)

  • Reliability and performances improvements in GPUs for HPC
    Sean Blanchard, High Performance Computing Center of the Los Alamos National Laboratory, USA
  • GPU reliability experimental assessment
    Paolo Rech, from Universidade Federal do Rio Grande do Sul, Brasil
  • Fault injection vs. AVF modeling/simulation in GPUs
    David Kaeli, Northeastern University, Boston, MA, USA

09:50-10:50 IP Session 10C: Reliability and Test Topics in Memories and Storage Systems
Room: Buena Vista/ Sutter Home
Organizer: Srivaths Ravi (TI, India) and Cheng Wen Wu (National Tsing Hua University)
Moderator: Srivaths Ravi (TI, India)

  • Reliability and Fault Tolerance in Storage Systems
    Manuel d’Abreu (Self, USA)
  • ATE Screening Methodologies for Ferroelectric RAM
    Scott Leisen , Bill Kraus & Jon Nafziger (Texas Instruments, USA)
  • SRAM speed binning with memory BIST
    Rei-Fu Huang , Chin-Lung Su, Ching-Yi Chee, Mango C.-T. Chao, and Hao-Yu Yang (Mediatek, China)

10:50-11:10 BREAK

11:10-12:10 Session 11A: ATPG and TEST Compression
Room: Hans Kornell
Moderator: Kazumi Hatayama, Gunma University, Japan

  • Multi-Cycle Circuit Parameter Independent ATPG for Interconnect Open Defects
    Dominik ERB (University of Freiburg – Germany), Karsten SCHEIBLER (University of Freiburg – Germany), Matthias SAUER (University of Freiburg – Germany), Sudhakar REDDY (University of Iowa , USA), Bernd BECKER (University of Freiburg – Germany)
  • Test Vector Omission with Minimal Sets of Simulated Faults
    Irith POMERANZ (Purdue University, USA)
  • Test Compaction by Test Cube Merging for Four-Way Bridging Faults
    Irith POMERANZ (Purdue University, USA)

11:10-12:20 Special Session 11B: Is Design-for-Security the new DFT?
Room: Freemark Abbey
Organizer and Moderator: Rob Aitken (ARM, USA)

Panelists:

  • Subhasish Mitra, Stanford
  • Mark Tehranipoor, U Connecticut
  • Steve Trimberger, Xilinx
  • Ron Perez, Rambus, Cryptography Research

11:10-12:10 IP Session 11C: Advanced Scan Methodologies
Room: Buena Vista/ Sutter Home
Organizer: Janusz Rajski (Mentor Graphics, USA)
Moderator: Nilanjan Mukherjee (Mentor Graphics, USA)

  • Practical Aspects of Hierarchical Test Implementation
    Vivek Chickermane (Cadence, USA)
  • ASIC Test Cost Reduction Using Advanced Scan Techniques
    Kamlesh Pandey (Broadcom, USA)
  • An IJTAG (IEEE1687) based Method to Automate ATPG Setup for an SoC with Complex Embedded Test Access Infrastructure
    Tassanee Payakapan, Senwen Kan, Ken Pham, Adam Abadir (AMD, USA)

12:20-13:40 LUNCH BREAK

13:40-14:40 Session 12A: DFT and ATPG
Room: Hans Kornell
Moderator: Rohit Kapur (Synopsys, USA)

  • Testing Cross Wire Opens within Complex Gates
    Chao HAN (Auburn University, USA), Adit SINGH (Auburn University, USA)
  • A Definition of the Number of Detections for Faults with Single Tests in a Compact Scan-Based Test Set
    Irith POMERANZ (Purdue University, USA)
  • Efficient Built-in Self Test of Regular Logic Characterization Vehicles
    Benjamin NIEWENHUIS (Carnegie Mellon University, USA), Shawn BLANTON (Carnegie Mellon Univ., Pittsburgh, USA)

13:40-15:10 Special Session 12B:  IOT – RELIABLE? SECURE? OR DEATH BY A BILLION CUTS?
Room: Freemark Abbey
Organizer: Suriyaprakash Natarajan, Sreekumar Kodakara (Intel, USA)

Panelists:

  • Mei Jiang (Hewlett Packard, USA)
  • Sridharan Ranganathan (Intel, USA)
  • Rob Aitken (ARM, USA)
  • Bill Eklow (Cisco, USA)
  • Umit Ogras (ASU)

13:30-15:10 Session 12C Hot Topic: Hierarchical Testing
Room: Buena Vista/ Sutter Home
Organizer: Yervant Zorian (Synopsys, USA)
Participants:

  • TBA
    Chartutosh Dixit (Avagotech, USA)
  • Hierarchical test solution for faster verification and reduced test time
    Arun Kumar (Synopsys, USA)
  • Surpassing area, speed, power and test coverage of memory BIST adopting alternative architectural approach.
    Gevorg Torjyan (Marvell, USA)