Monday, 4/29/13

7:30 - 8:30   Registration & Breakfast

8:30 - 10:30   Plenary Session - Empire

• Welcome Message
  M. Renovell (LIRMM), General Chair
• Program Introduction
  Y. Makris (University of Texas at Dallas), Program Chair
• Keynote address: The Integration Train: Will Test Challenges Impede Progress Read more...
  K. Hansen (Vice President and Chief Technology Officer, Freescale Semiconductor Inc.)
• Invited Keynote: Are the Test Solutions Ready to take up the Challenges posed by Advanced Technology R&D? Read more...
  S. Kengeri (Vice President of Advanced Technology Architecture, GLOBALFOUNDRIES)
• Awards Presentation
  Y. Zorian (Synopsys), Ex-Officio

10:30 - 10:50   Break

10:50 - 12:10   Sessions 1

• Experiments and Analysis to Characterize Logic State Retention Limitations in 28nm Process Node
  S. Dasnurkar, N. Kulkarni, H. Nguyen, R. Lavakumar, A. Datta, M. Abu-Rahma, P. Seeram, P. Bhadri, M. Cai, S. Sengupta (Qualcomm)
• Testing Retention Flip-flops in Power-Gated Designs
  H.-W. Hsu, S.-H. Kuo, W.-H. Chang (NCTU), S.-H. Chen, M.-T. Chang (Global Unichip), M. Chao (NCTU)
• Power Supply Noise Control in Pseudo Functional Test
  D. Walker, T. Zhang (Texas A&M)
• Finding Best Voltage and Frequency to Shorten Power-Constrained Test Time
  P. Venkataramani, S. Sindia, V. Agrawal (Auburn University)

• Improving Test Generation by Use of Majority Gates
  P. Wohl, J. Waicukauski (Synopsys)
• SOC Test Compression Scheme Using Sequential Linear Decompressors with Retained Free Variables
  S. Muthyala, N. Touba (University of Texas, Austin)
• Selection of Tests for Outlier Detection
  H. Bossers, J. Hurink, G. Smit (University of Twente)
• Tracing the Best Test Mix through Multi-Variate Quality Tracking
  B. Arslan, A. Orailoglu (University of California, San Diego)

• Pre-/Post-Silicon Validation - Opportunities for Commonality, Essential Differences
  C. Meissner (IBM)
• Emulation: "Shift Left" Enabler for Validation
  M. Goveas (Intel)
• SOC Validation and IP
  R. Aitken (ARM)
• Unique SOC Electrical Validation Challenges
  V. Saxena (Intel)

12:10 - 13:30   Lunch

13:30 - 14:30   Sessions 2

• Measurement of Envelope/Phase Path Delay Skew and Envelope Path Bandwidth in Polar Transmitters
  J. W. Jeong, S. Ozev (Arizona State University), S. Sen, T. M. Mak (Intel)
• Defect-Oriented Non-Intrusive RF Test Using On-Chip Temperature Sensors
  L. Abdallah, H. Stratigopoulos, S. Mir (TIMA), J. Altet (UPC)
• Novel Estimation Method of EVM with Channel Correction for Linear Impairments in Multistandard RF Transceivers
  K. Asami, T. Shimuta, T. Kurihara (Advantest)

Speaker: S. Hassoun (Tufts University)

• Flash Memory - What Can Go Wrong and How to Screen For It
  M. D'Abreu (SanDisk)
• Challenges and Opportunities - Embedded Memory Testing
  Z. Bao (Intel)
• SRAM Yield Modeling for Optimal Redundancy in Complex SOCs
  C. Riccobene (LSI)

14:30 - 14:50   Break

14:50 - 15:50   Sessions 3

• An Effective Solution for Building Memory BIST Infrastructure Based on Fault Periodicity
  G. Harutyunan, S. Shoukourian, V. Vardanian, Y. Zorian (Synopsys)
• A Built-in Scheme for Testing and Repairing Voltage Regulators of Low-Power SRAMs
  L. Bonet Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri-Sanial, A. Virazel (LIRMM), N. Badereddine (Intel)
• Testing of a Low-VMIN Data-Aware Dynamic-Supply 8T SRAM
  C.-W. Lin, C.-Y. Huang, M. Chao (NCTU)

Contestants:
• P. Das (University of Southern California)
  Thesis Title: A Variation Aware Resilient Framework for Post-silicon Delay Validation of High Performance Circuits
  Advisor: S. Gupta
• K. Huang (TIMA)
  Thesis Title: Fault Modeling and Diagnosis for Nanometric Analog/Mixed-Signal/RF Circuits
  Advisors: S. Mir & H. Stratigopoulos
• Y. Li (Stanford University)
  Thesis Title: Online Self-Test, Diagnostics, and Self-Repair for Robust System Design
  Advisor: S. Mitra
• D. Maliuk (Yale University)
  Thesis Title: Analog Neural Classifiers for Built-In Self-Test of Analog/RF Circuits
  Advisor: Y. Makris
• B. Noia (Duke University)
  Thesis Title: Design-for-Test and Test Optimization of TSV-based 3D Stacked ICs
  Advisor: K. Chakrabarty
• E. Yilmaz (Arizona State University)
  Thesis Title: Efficient Test Strategies for Analog/RF Circuits
  Advisor: S. Ozev

• Paradigm Shift in High Speed I/O Design for Test and Manufacturing: Is Loopback Test Sufficient?
  S. Abdennadher (Intel)
• Improving Testability for High Speed SERDES
  L. Ying (Broadcom)
• Increasing Analog Debug Efficiency on High Speed Interfaces by 2x in Today's SoCs
  S. Modekurty (Intel)

15:50 - 16:10   Break

16:10 - 17:40   Sessions 4

• Reliability in Mobile Applications
  R. Aitken (ARM)
• System Level Soft Error Testing
  R. Wong (Cisco)
• Models and Tools for Cost Effective Reliable Solutions
  O. Lauzeral (iROC)

• Forecast METER
  R. Blanton (Carnegie Mellon University)
• Functional Observable Fault (FOF): A Fault Model for Logical Bugs as well as Faults
  M. Fujita (University of Tokyo)
• Impact of Process Variation on Delay Test Quality
  K. Hatayama (NAIST)
• Accelerating NBTI Aging to Wear out Digital Circuits
  N. Karimi (NYU-Poly)
• Privilege Escalation Attack through Address Space Identifier Corruption in Untrusted Modern Processors
  M. Maniatakos (NYU-AD)
• Radiation Tolerant Reconfigurable Payload Data Processing Units for Space Applications
  A. Paschalis (University of Athens)
• Delay Faults: Are We Looking for the Right Ones?
  A. Singh (Auburn University)
• Techniques to Leverage Test Speed of Wide Band Circuit/System
  T. Xia (University of Vermont)

• Testing Method of Chip-to-Chip Interconnection for 3D LSI Chip Stacking System
  M. Aoyagi (AIST)
• Challenges in Design and Test for 3D Memory: TSV RAM, 3D Nonvolatile RAM and 3D NAND Flash
  M.-F. Chang (NTHU)
• 3-D IC Design and Test Activities in ITRI
  D.-M. Kwai (ITRI)

Tuesday, 4/30/13

7:30 - 8:30   Registration & Breakfast

8:30 - 9:30   Sessions 5

• Extending Pre-silicon Delay Models for Post-silicon Tasks: Validation, Diagnosis, Delay Testing and Speed Binning
  P. Das, S. Gupta (University of Southern California)
• Path Selection Based On Static Timing Analysis Considering Input Necessary Assignments
  B. Yao (Purdue University), A. Sinha (Intel)
• Scalable Dynamic Technique for Accurately Predicting Power-Supply Noise and Path Delay
  S. Rao, R. Robucci, C. Patel (University of Maryland, Baltimore County)

• Contactless Test Access Mechanism for TSV Based 3D ICs
  R. Rashidzadeh (University of Windsor)
• 3D-IC Interconnect Test, Diagnosis, and Repair
  C.-C. Chi, C.-W. Wu (NTHU), M.-J. Wang, H.-C. Lin (TSMC)
• Testing of Flow-Based Microfluidic Biochips
  K. Hu (Duke University), T.-Y. Ho (NCKU), K. Chakrabarty (Duke University)

• Hardware Errors at Cloud-Scale: Abort, Retry or Ignore?
  K. Vaid (Microsoft)
• Predictive Analytics for Resilient Cloud Support in Mission Critical Applications
  P. Kudva (IBM)
• Increasing Relevance of System Level RAS Features in the New Cloud
  M. Natu (Intel)

9:30 - 9:50   Break

9:50 - 10:50   Sessions 6

• A Framework for Low Overhead Hardware Based Runtime Control Flow Error Detection and Recovery
  A. Chaudhari, J. Park, J. Abraham (University of Texas, Austin)
• Trading Off Area, Yield and Performance via Hybrid Redundancy in Multi-Core Architectures
  Y. Gao, Y. Zhang, D. Cheng, M. Breuer (University of Southern California)
• Combining Checkpointing and Scrubbing in FPGA-based Real-Time Systems
  A. Sari, M. Psarakis (University of Piraeus), D. Gizopoulos (University of Athens)

• An IDDQ BIST Approach to Characterize Phase-Locked Loop Parameters
  S. Maltabas (University of Massachusetts, Lowell), O. Ekekon (Intel), K. Kulovic (Maxim), A. Meixner (Intel), M. Margala (University of Massachusetts, Lowell)
• A Programmable BIST Design for PLL Static Phase Offset Estimation and Clock Duty Cycle Detection
  S.-W. Hsiao, N. Tzou, A. Chatterjee (Georgia Institute of Technology)
• Reduced Code Linearity Testing of Pipeline ADCs in the Presence of Noise
  A. Laraba, H. Stratigopoulos, S. Mir (TIMA), H. Naudet, G. Bret (STMicroelectronics)

• A New Approach to Reduce Test Cost using Shared I/O-based Pin Reduction
  K.-Y. Chung (Samsung)
• Various Test Compression Methods in Hierarchical Test
  H. Konuk (Broadcom)
• Achieving Higher Test Compression - Now and the Future
  Y. Dong (AMD)

10:50 - 11:10   Break

11:10 - 12:10   Sessions 7

• Enhanced Algorithm of Combining Trace and Scan Signals in Post-Silicon Validation
  K. Han (Samsung), J.-S. Yang (Intel), J. Abraham (University of Texas, Austin)
• Distributed Dynamic Partitioning Based Diagnosis of Scan Chain
  Y. Huang (Mentor Graphics), X. Fan (University of Iowa), H. Tang, M. Sharma, W.-T. Cheng, B. Benware (Mentor Graphics), S. Reddy (University of Iowa)
• RAVAGE: Post-Silicon Validation of Mixed-Signal Systems Using Genetic Stimulus Evolution and Model Tuning
  B. Muldrey, M. Giardino, S. Deyati, A. Chatterjee (Georgia Institute of Technology)

Presenter: M. Alioto (University of Siena)

• Critical Path Monitors: Calibration and Modeling Strategies in a DVFS Setting
  A. Drake (IBM)
• Built-in Calibration and Compensation in Low-Cost Transceiver SoCs
  O. Eliezer (Xtendwave)
• Challenges of Trimming a PSoC in a Low Cost Manufacturing Flow
  P. Berndt (Cypress)

12:10 - 13:30   Lunch

13:30 - 15:00   Sessions 8

Contestants:
• P. Das (University of Southern California)
  Thesis Title: A Variation Aware Resilient Framework for Post-silicon Delay Validation of High Performance Circuits
  Advisor: S. Gupta
• K. Huang (TIMA Lab)
  Thesis Title: Fault Modeling and Diagnosis for Nanometric Analog/Mixed-Signal/RF Circuits
  Advisors: S. Mir & H. Stratigopoulos
• Y. Li (Stanford)
  Thesis Title: Online Self-Test, Diagnostics, and Self-Repair for Robust System Design
  Advisor: S. Mitra
• D. Maliuk (Yale University)
  Thesis Title: Analog Neural Classifiers for Built-In Self-Test of Analog/RF Circuits
  Advisor: Y. Makris
• B. Noia (Duke University)
  Thesis Title: Design-for-Test and Test Optimization of TSV-based 3D Stacked ICs
  Advisor: K. Chakrabarty
• E. Yilmaz (Arizona State University)
  Thesis Title: Efficient Test Strategies for Analog/RF Circuits
  Advisor: S. Ozev

Presenters: M. D'Abreu (SanDisk) & X. Hu (SanDisk)

• A Study on the Effectiveness of Trojan Detection Techniques using a Red Team Blue Team Approach
  X. Zhang, K. Xiao, M. Tehranipoor (University of Connecticut), J. Rajendran, R. Karri (NYU-Poly)
• A Multi-Parameter Functional Side-Channel Analysis Method for Hardware Trust Verification
  C. Bell, M. Lewandowski, S. Katkoori (University of South Florida)
• Experiences In Side Channel and Testing Based Hardware Trojan Detection
  D. Hély, J. Martin, G. Triana, S. Mounier, E. Rivière, T. Sahuc, J. Savonet, L. Soundararadjou (Grenoble INP)
• A Multi-Faceted Approach to FPGA-Based Trojan Circuit Detection
  M. Patterson, A. Mills, R. Scheel, J. Tillman, E. Dye, J. Zambreno (Iowa State University)
• Towards a Cost-Effective Hardware Trojan Detection Methodology
  R. Paseman, A. Orailoglu (University of California, San Diego)

15:00 - 15:30   Break

15:30 - 22:00   Social Event

Wednesday, 5/1/13

7:30 - 8:30   Registration & Breakfast

8:30 - 9:30   Sessions 9

• A Hybrid ECC and Redundancy Technique for Reducing Refresh Power of DRAMs
  J.-F. Li, Y.-C. Yu, C.-S. Hou, L.-J. Chang (NCU), C.-Y. Lo, D.-M. Kwai, Y.-F. Chou (ITRI), C.-W. Wu (NTHU)
• An Iterative Diagnosis Approach for ECC-based Memory Repair
  P. Papavramidou, M. Nicolaidis (TIMA)
• Investigation of Gate Oxide Short in FinFETs and the Test Methods for FinFET SRAMs
  C.-W. Lin, M. Chao (NCTU), C.-C. Hsu (ITRI)

Presenters: E. Larsson (Lund University) & M. Keim (Mentor Graphics)

• Electrical Characterization Needs for Rapid Yield Learning and Monitoring at Advanced Technology Nodes
  K. Michaels (PDF Solutions)
• Process Technology Disruptions and the Evolution of Diagnosis Driven Yield Analysis (DDYA)
  B. Benware (Mentor Graphics)
• Collaborative Yield Improvement
  R. Madge (GLOBALFOUNDRIES)

9:30 - 9:50   Break

9:50 - 10:50   Sessions 10

• On the Investigation of Built-in Tuning of RF Receivers using On-chip Polyphase Filters
  F. Haddad, W. Rahajandraibe, H. Aziza, J. M. Portal, K. Castellani-Coulie (Aix-Marseille University)
• On-Chip Circuit for Measuring Multi-GHz Clock Signal Waveforms
  K. Jenkins (IBM)
• Low-Cost Multi-Channel Testing of Periodic Signals Using Monobit Receivers and Incoherent Subsampling
  T. Moon (Georgia Institute of Technology), H. W. Choi (Samsung), A. Chatterjee (Georgia Institute of Technology)

• Chip-level Modeling and Analysis of Electrical Masking of Soft Errors
  M. Ebrahimi, S. Kiamehr, F. Firouzi, M. Tahoori (KIT)
• Identification of Critical Variables using an FPGA-based Fault Injection Framework
  A. Riefert, J. Mueller, M. Sauer, W. Burgard, B. Becker (University of Freiburg)
• RSAK: Random Stream Attack for Phase Change Memory in Video Applications
  Y. Fang, H. Li, X. Li (Chinese Academy of Sciences)

• A Synergistic Approach to Structured & Efficient At-Speed Testing
  M. Amodeo (Cadence)
• Microprocessor World's Transition into At-Speed Scan Delay Debug
  S. Vora (Intel)
• Improving At-Speed Test Quality with the Small Delay Defect Model
  J. Colburn (Nvidia)

10:50 - 11:10   Break

11:10 - 12:10   Sessions 11

• Post-DfT-Insertion Retiming for Delay Recovery on Inter-Die Paths in 3D ICs
  B. Noia, K. Chakrabarty (Duke University)
• Allocation of RAM Built-In Self-Repair Circuits for SOC Dies of 3D ICs
  J.-F. Li, C.-S. Hou (NCU)
• Test-Cost Optimization and Test-Flow Selection for 3D-Stacked ICs
  M. Agrawal, K. Chakrabarty (Duke University)

• Multi-Methodology, Advanced On-Chip-Clocking for Structural Tests
  S. Ganta (Broadcom)
• EDA Directions in On-Chip Clocking Support
  T. Ayres (Synopsys)
• CISCO Experiences with Internal Capture for Both Stuck-at and Speed Faults: Tester Interface, Test Volume, Coverage and Speed Characterization
  C. Njinda (Cisco)

• Software/Hardware Co-Design Reliability Solutions at the System Level
  M. Kumar (Intel)
• Blue Gene/Q - Design for Reliability in a Very Large Computing System
  R. Haring (IBM)
• Challenges of Deep Sub-micron Digital Design
  S. Kosonocky (AMD)

12:10 - 13:30   Lunch

13:30 - 15:00   Sessions 12

• Can't Fake it Unless they Make it!
  F. Koushanfar (Rice University)
• Counter-fighting Counterfeiting with Hardware Intrinsic Security
  P. Tuyls (Intrinsic-ID)
• Lifecycle Counterfeit Detection Using Silicon Manufacturing Variations
  M.-D.Yu (Verayo)

Panelists: J. Abraham (University of Texas, Austin), G. Roberts (McGill University),
          S. Natarajan (Intel), D. Ciplickas (PDF Solutions)