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Monday, May 2nd
07:30am-09:00am Registration and Breakfast
9:00am-11:00am Plenary Session
| Welcome message: | Cecilia Metra, General Chair |
| Keynote Address: | "Cost-Effective Innovation to Address Next Generation Challenges in Design and Test", Sanjiv Taneja, Vice President, Cadence |
| Program Introduction: | Claude Thibeault, Program Chair |
| Invited Keynote: | "Variability, Design Margining, Low Power, Yield and Reliability: Challenges and Opportunities in Highly Scaled CMOS Geometries", Fadi Kurdahi, University of California Irvine |
| Invited Keynote: | "Designing Single-Chip Massively Parallel Tera-Device Processors: Towards the Terminator Chip", Michael Nicolaidis, TIMA |
| Awards Presentation: | Yervant Zorian:
TTTC Most Successful Technical Meeting Award
TTTC Most Populous Technical Meeting Award
VTS 2010 Best Paper Award
VTS 2010 Best Innovative Practices Award
VTS 2010 Best Special Session Award
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11:00am-11:15am Break
11:15am-12:15am Sessions 1
Session 1A: Post-Silicon Debug & Customer Returns
Moderator: Mike Rodgers - Mike Rodgers Consulting
- Understanding Customer Returns From A Test Perspective
N. SUMIKAWA, D. DRMANAC, L.-C.WANG - UC Santa Barbara, L. WINEMBERG, M. ABADIR - Freescale Semiconductor
- A Distributed AXI-based Platform for Post-Silicon Validation
M. H. NEISHABURI, Z. ZILIC - McGill University
- Efficient Trace Data Compression Using Statically Selected Dictionary
K. BASU, P. MISHRA - University of Florida
Session 1B: 3D ICs
Moderator: M. LAISNE - Qualcomm
- A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs
Y.-J. HUANG, J.-. LI - National Central University, J.-J. CHEN, D.-M. KWAI, Y.-F. CHOU, C.-W. WU - National Tsing Hua University
- Scan Chain and Power Delivery Network Synthesis for Pre-Bond Test of 3D ICs
S. PANTH, S. K. LIM - Georgia Institute of technology
- Exploiting Rotational Symmetries for Improved Stack Yields in W2W 3D-SICs
E. SINGH - Stanford University
IP Session 1C: Test and Characterization of High-Speed Circuits
Organizer: Saghir Shaikh - Broadcom
Moderator: B. Gravens - Teradyne
Abstract: Test, validation and characterization of high-speed circuits is a becoming a complex issue due to increase in circuit marginality, higher fallout, and more complex test solutions. The issue is compounded by the complex interactions between packaged components; interconnect design and customer board designs. This session will address the challenges in characterizing high-speed circuits including PLLs and SERDES. It describes test methodologies to overcome those challenges using industrial test cases.
- Characterization Of The Digital PLLs On An 8-Core Microprocessor Using Electrical And Optical Techniques
K. STAWIASZ, K. JENKINS, P. SONG, F. STELLARI, J. TIERNO, A. RYLAKOV, D. FRIEDMAN - IBM
- Challenges in High Volume Manufacturing Test and System Correlation for High Speed IO
A. MEIXNER - Intel Corporation
- High-Speed SerDes Characterization
D. HONG, M. ISAACS - Broadcom
12:15pm-01:45pm Lunch & Awards
01:45pm-02:45pm Sessions 2
Session 2A: Power Issues in Test
Moderator: P. Girard - LIRMM
- Expedited Response Compaction for Scan Power Reduction
S. M. SAEED - New York University PI, O. SINANOGLU - New York University at Abu Dhabi
- Leakage Power Profiling and Leakage Power Reduction using DFT Hardware
R. SETHURAM, K. ARABI, M. ABU-RAHMA - Qualcomm
- Levelized Low Cost Delay Test Compaction Considering IR-Drop Induced Power Supply Noise
Z. JIANG, Z. WANG - Texas A&M University, J. WANG - AMD, D. M. H. WALKER - Texas A&M University
Session 2B: Analog, Mixed-Signal & RF Test /Diagnosis
Moderator: J. Abraham - U of Texas Austin
- Automatic Test Stimulus Generation for Accurate Diagnosis of RF Systems Using Transient Response Signatures
A. BANERJEE, S. SEN, S. DEVARAKOND, A. CHATTERJEE - Georgia Institute of Technology
- Non-Linear Analog Circuit Test and Diagnosis under Process Variation using V-Transform Coefficients
S. SINDIA, V. AGRAWAL - Auburn University, V. SINGH - Indian Institute of Science
- A Diagnosis Testbench of Analog IP Cores Against On-Chip Environmental Disturbances
T. HASHIDA, Y. ARAGA, M. NAGATA - Kobe University
IP Session 2C: On Chip Parametric Sensors
Organizer: Aman Kokrady - Texas Instruments
Moderator: M. Margala - U. Massachusetts Lowell
Abstract: Traditionally, structures are placed in scribe line to measure critical parameters. These structures are used both as wafer acceptance metric and also as a debug aid to identify systematic process defects. With shrinking technology, increasing die-sizes and increasing variability (both inter and intra die), use of on-chip parametric sensors is gaining importance. This session explores different facets of parametric sensors and their growing importance.
- On Chip Parametric Structures: 40nm, a case study
C. FRANK, K. AMAN, G. ABHISHEK, K. RAJESH, M. NANDU, K. TAE, D. RAJEELA, T. KEVIN - Texas Instruments
- Minimally Invasive Methods for Characterizing Within-Die Variation
K. AGARWAL - IBM, J. PLUSQUELLIC - University of New Mexico
- On-die monitors for measuring the impact of dynamic voltage, temperature, and aging variations on processor performance
C. TOKUNAGA, K. BOWMAN, J. TSCHANZ - Intel Corporation
02:45pm-03:00pm Break
03:00pm-04:00pm Sessions 3
Session 3A: Delay & Performance Test 1
Moderator: R. Tekumalla - LSI
- Case Study: Efficient SDD Test Generation for Very Large Integrated Circuits
K. PENG, F. BAO - University of Connecticut, G. SHOFNER, L. WINEMBERG - Freescale Semiconductor, M. TEHRANIPOOR - University of Connecticut
- Static Test Compaction for Delay Fault Test Sets Consisting of Broadside and Skewed-Load Tests
I. POMERANZ - Purdue University
- Efficient and Product-Representative Timing Model Validation
E. J. JANG - University of Texas at Austin, A, GATTIKER, S. NASSIF - IBM, J. ABRAHAM - University of Texas at Austin
Special Session 3B: Hot Topic: Multifaceted Approaches for Field Reliability
Organizer: Y. SATO - Kyushu Institute of Technology
Moderator: Y. SATO - Kyushu Institute of Technology
Abstract: Field Reliability is a so complex problem that a single approach is not enough. Three distinguished researchers address their various state-of-the-art approaches, which include debug, soft-error and field test. They will also raise an issue of testing.
- Programmability based approach to post-silicon debug and rectification
M. FUJITA - Tokyo University
- An EDA tool chain for soft-error tolerant VLSI design
Y. MATSUNAGA - Kyushu University
- Accurate and Efficient SoC Field Test for Failure Prediction
M. INOUE - Nara Institute of Science and Technology, S. KAJIHARA - Kyushu Institute of Technology
IP Session 3C: Advanced Methods for Leveraging New Test Standards
Organizer: M. LAISNE - Qualcomm
Moderator: A. Cron - Synopsys
Abstract: This session explores how newly introduced standards are supporting innovative industry practices. First, a new update for 1149.1, including new instructions, extensions, and a new procedural language, is reviewed. Next, techniques for implementing concurrent test using P1687 are described. Finally, a method is examined, using P1581, for connectivity testing of ICs with no boundary scan.
- Innovative practices with the new IEEE P1149.1-2011 JTAG update
C.J. CLARK - Intellitech Corp., C. PYRON - Freescale
- Test Concurrency using P1687
S. ZUO, M. LAISNE - Qualcomm
- IEEE P1581 - Simplifying Connectivity Tests for Complex Memories and other Non-Boundary Scan Devices
H. EHRENBERG - Goepel
04:00pm-04:15pm Break
04:15pm-05:15pm Sessions 4
Special Session 4A: New Topics
Organizers: B. Kaminska - Simon Fraser University, B. Courtois - CMP
Moderator: B. Courtois - CMP
- Parametric Yield and Reliability of 3D Integrated Circuits: New Challenges and Solutions
Siddharth Garg - Waterloo, Diana Marculescu - Carnegie Mellon
Session 4B: Security
Moderator: A. Davoodi - U. Wisconsin
- Security-Aware SoC Test Access Mechanisms
K. ROSENFELD - Google, E. GAVAS, R. KARRI - New York University PI
- Design and Analysis of Ring Oscillator Based Design-for-Trust Technique
J. RAJENDRAN, V. JYOTHI - New York University PI, O. SINANOGLU - New York University at Abu Dhabi, R. KARRI - New York University PI
- Embedded mini-tutorial: Emerging Hardware-Oriented Security and Trust Issues in the Design and Fabrication of Integrated Circuits
J. PLUSQUELLIC - University of New Mexico, M. TEHRANIPOOR - University of Connecticut
IP Session 4C: The Buck Stops With Wafer Test: Dream Or Reality?
Organizers: S. NATARAJAN - Intel Corporation, A. SINHA (AMD)
Moderator: H. MANHAEVE - QStar
Abstract: Even though the KGD problem has been discussed since the mid 90's, the problem becomes more and more difficult with every new process node and new design requirement. There is need to develop high quality tests, on-die DFX instrumentation, and reliability screens that can be applied at wafer sort, given pin and test time constraints. The quality of tests used at wafer-sort should not only be enough to reject bad parts, but enable estimation of the performance/power of packaged parts on a system. This session explores challenges of Wafer testing.
- A Case for Known Good Die
K. ARABI - Qualcomm
- Challenges with Achieving KGD for High Performance Products
T. M. MAK - Intel Corporation
- Mixed Wafer Test Strategies for the Automotive, 0 DPPM Market
L. WINEMBERG - Freescale Semiconductor
08:00pm-09:30pm Sessions 5
Special Session 5A: Apprentice, Season 4
Organizers: K. S. KIM - Samsung, R. ROY - Atrenta
Abstract: The main objective of this active "panel" is to increase technical interaction among attendees. Team leaders will recruit participants to their team. Each team will try to clearly articulate the problems and come up with ways to solve this problem in the form of new business proposal. The teams will present their findings and business proposals in front of judges at Session 9B. The winning team will be announced during the social event.
Special Session 5B: Panel: How Much Toggle Activity Should We Be Testing With?
Organizer: X. WEN, Kyushu Institute of Technology
Moderator: M. TEHRANIPOOR, University of Connecticut
Abstract: With the stress on reducing toggle activity during test one might question - Have we gone too far? Should we reduce toggle activity below functional? Should we even plan for many test sets with different toggle activity. Is the power problem solved by the existing DFT and ATPG solutions? What next for power? What is missing in today's solutions?
Panelists:
- R. KAPUR - Synopsys
- A. BHAT - Texas Instruments India
- A. MAJUMDAR - Advanced Micro Devises
- L. WINEMBERG - Freescale
Tuesday, May 3rd
07:00am-08:00am Breakfast
08:00am-09:00am Sessions 6
Session 6A: Delay & Performance Test 2
Moderator: K. Balakrishnan - AMD
- A Novel Mechanism for Speed Characterization During Delay Test
A. MAJUMDAR, A. SINHA, N. PATEL , R. SETTY, Y. DONG, S.-H. CHOU - AMD
- An Efficient Method to Screen Resistive Opens under Presence of Process Variation
S. WANG - Samsung Austin Semiconductor
- On Clustering of Undetectable Transition Faults in Standard-Scan Circuits
I. POMERANZ - Purdue University
Session 6B: Memory Test and Repair
Moderator: Anne Meixner - Intel
- Designing a Fast and Adaptive Error Correction Scheme for Increasing the Lifetime of Phase Change Memories
R. DATTA, N. TOUBA - University of Texas at Austin
- Programmable Extended SEC-DED Codes for Memory Errors
V. GHERMAN, S. EVAIN, F. AUZANNEAU, Y. BONHOMME - CEA LIST
- Training -Based Forming Process for RRAM Yield Improvement
H.-C. SHIH, C.-Y. CHEN, C.-W. WU - National Tsing Hua University , C.-H. LIN, S.-S. SHEU - Industrial Technology Research Institute
IP Session 6C: The Bang For The Buck With Resiliency: Yield Or Field?
Organizers: S. NATARAJAN - Intel Corporation, A. SINHA - AMD
Moderator: S. Venkataraman - Intel
Abstract: This session explores the state of the art in industrial designs that employ resilient features either for improving manufacturing yield or operating in the field, and the cost/benefit trade-offs in each case. The resilient features to be discussed are not restricted to any particular design abstraction and can span device-level to the software stack. The session would also address these trade-offs in the context of mixed-signal designs due to their increased integration in current/future systems.
- Resilient Circuits for Improving Microprocessor Performance and Energy Efficiency
C. TOKUNAGA - Intel Corporation
- Resiliency: An IP Design Perspective
V. CHANDRA - ARM
- High Performance Mixed-Signal/RF: Yield Recovery via Post-Manufacture Tuning
A. Chatterjee - Georgia Tech
09:00am-09:15am Break
09:15am-10:15am Sessions 7
Session 7A: Low-Power IC Test
Moderator: A.Singh - Auburn University
- Modified Flip-flop Architecture to Reduce Hold Buffers and Peak Power during Scan Shift Operation
P. NARAYANAN, R. K. MITTAL, V.SINGHAL, S. PODDUTUR, P. SABBARWAL - Texas Instruments India
- Power-Safe Test Application Using An Effective Gating Approach Considering Current Limits
W. ZHAO, M. TEHRANIPOOR - University of Connecticut, S. CHAKRAVARTY - LSI
- Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing
X. WEN, K. ENOKIMOTO, K. MIYASE, Y. YAMATO - Kyushu Institute of Technology , M. KOCHTE - University of Stuttgart, S. KAJIHARA - Kyushu Institute of Technology, P. GIRARD - LIRMM, M.TEHRANIPOOR - University of Connecticut
Session 7B: Defects & Faults Modelling & Simulation
Moderator: D. M. H. WALKER - Texas A&M University
- SLIDER: A Fast and Accurate Defect Simulation Framework
W. C. TAM, R. Shawn BLANTON - Carnegie Mellon University
- An Industrial Case Study of Analog Fault Modeling
E. YILMAZ - Arizona State University, A.MEIXNER - Intel, S. OZEV - Arizona State University
- A New Methodology for Realistic Open Defect Detection Probability Evaluation under Process Variations
J. MORENO, V. H. CHAMPAC - INAOE, M. RENOVELL - LIRMM
10:15am-10:30am Break
10:30am-11:30am Sessions 8
Session 8A: Aging, Transients & Soft Errors
Moderator: T. Chakraborty - Qualcomm
- Impact of the Application Activity on Intermittent Faults in Embedded Systems
J. GUILHEMSANG, O. HERON, N. VENTROUX, O. GONÇALVES - CEA LIST, A. GIULIERI - LEAT
- An Analytical Method for Estimating SET Propagation
S. GANGADHAR, S. TRAGOUDAS - Southern Illinois University
- Adaptive Error-Prediction Flip-flop for Performance Failure Prediction with Aging Sensors
C. MARTINS, J. SEMIAO - University of Algarve, J. VAZQUEZ, V. H. CHAMPAC - INAOE, M. SANTOS, I. C. TEIXEIRA, J.P. TEIXEIRA - IST UTL
Special Session 8B: New Topic: Solar Cells
Organizers: B. Kaminska - Simon Fraser University, B. Courtois - CMP
Moderator: B. Kaminska - Simon Fraser University
- Characterization of Multi-Junction Solar Cells Under High Concentration using Flash and Continuous Solar Simulators
J. Wheeldon - Ottawa
11:30am-12:45pm Lunch
12:45am-02:15pm Sessions 9
Special Session 9A: Best Doctoral Thesis
Organizer: S. Vasudevan - U. of Illinois at Urbana-Champaign
Moderator: Y. Makris - Yale University
Abstract: This is one of the semifinals of doctoral student contest for E.J. McCluskey Doctoral Thesis Award, whose final will be held at ITC 2011.
Special Session 9B: Apprentice Judgment
Organizers: K. S. KIM - Samsung, R. ROY - Atrenta
Abstract: This is the judging session of Session 5A. The teams will present their findings and business proposals in front of judges. The winning team will be announced during the social event.
Judges:
- B. WINCHELL - Partner Ventures, Managing Director
- L. OLIPHANT - Intel, Director of Intel Capital
- Y. ZORIAN - Synopsys, VP
- A. MATHUR - CTO Calypto
Special Session 9C: Panel: Coverage Closure in SoC Verification: Are We Chasing a Mirage?
Organizer: S. Vasudevan - U. of Illinois at Urbana-Champaign
Moderator: S. Vasudevan - U. of Illinois at Urbana-Champaign
Abstract: With over 78% of designs being heterogeneous integrations of diverse components, SoCs are ubiquitous. This integration, though, brings with it the malaise of challenges in verification and validation. This panel will have specialists in verification/validation platforms targeted at the various development phases.
Panelists:
- H. Foster - Mentor Graphics
- P. Graykowski - Synopsys
- A. Mathur - Calypto
- B. Quinton - Veridae Systems
- C. Thibeault - ETS
02:30pm-10:00pm Social Event
Wednesday, May 4th
07:30am-08:30am Breakfast
08:30am-09:30am Sessions 10
Session 10A: Design for Testability 1
Moderator: Z. Navabi - Worcester Polytechnic
- A Scan Cell Architecture for Inter-Clock At-Speed Delay Testing
K. Y. CHO, R. SRINIVASAN - NVIDIA
- Design and Implementation of A Time-Division Multiplexing Scan Architecture Using Serializer and DeSerializer in GPU Chips
A. SANGHANI, B. YANG, C. LIU, K. NATARAJAN - NVIDIA
- Harmony Widget for X-Free Scan Testing
D. K. BHAVSAR - Intel Corporation
Session 10B: Error & Fault Tolerance 1
Moderator: M. Mohsenian - Intel
- Localization of Damaged Resources in NoC Based Shared-Memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure
Z. ZHANG, D. REFAUVELET, A. GREINER - University Pierre and Marie Curie, M. BENABDENBI - TIMA, F. PECHEUX - University Pierre and Marie Curie
- Exponent Monitoring for Low-Cost Concurrent Error Detection in Floating Point Unit Control Logic
M. MANIATAKOS, Y. MAKRIS - Yale University, P. KUDVA, B. FLEISCHER - IBM
- Enhancing Online Error Detection through Area-Efficient Multi-Site Implications
N. ALVES, Y. SHI - Brown University, J.DWORAK - Southern Methodist University, R.I. BAHAR - Brown University, K. NEPAL -Bucknell University
09:30am-09:45am Break
09:45am-10:45am Sessions 11
Session 11A: Design for Testability 2
Moderator: R. Jayabharathi - Intel
- Dynamic Scan Clock Control for Test Time Reduction Maintaining Peak Power Limit
P. SHANMUGASUNDARAM, V. AGRAWAL - Auburn University
- Structural Tests of Slave Clock Gating in Low Power Flip Flop
B. WANG, J. RAJARAMAN, K. SOBTI, D. LOSLI, J. REARICK - AMD
- Revival of Partial Scan: Test Cube Analysis Driven Conversion of Flip-Flops
N. ALAWADHI - Kuwait University, O. SINANOGLU - New York University at Abu Dhabi
Session 11B: Error & Fault Tolerance 2
Moderator: P. Berndt - Cypress Semiconductor
- Memory-based Embedded Digital ATE
D. LEE, S. P. PARK - Purdue University, A. GOEL- Broadcom, K. ROY - Purdue University
- A Unified Test Architecture for On-Line and Off-Line Delay Fault Detections
S. PEI, H. LI, X. LI - Chinese Academy of Sciences
- Design For Bit Error Rate Estimation of High Speed Serial Links
U. GUIN - Temple University, C.-H. CHIANG - Alcatel-Lucent
10:45am-11:00am Break
11:00am-12:00pm Sessions 12
Session 12A: ATPG & Compression
Moderator: A. Chandra - Synopsys
- An Efficient Test Data Volume Reduction Technique through Dynamic Patterns Mixing across Multiple Fault Models
S. ALAMPALLY - Texas Instruments India, R.T. VENKATESH, P. SHANMUGASUNDARAM - Auburn University, R.A. PAREKHJI - Texas Instruments India, V. AGRAWAL - Auburn University
- Low Coverage Analysis Using Dynamic Untestability Debug in ATPG
K. CHANDRASEKAR, S. BOMMU, S. SENGUPTA - Intel Corporation
- Prediction of Compression Bound and Optimization of Compression Architecture for Linear Decompression-based Schemes
J. LI - Tsinghua University, Y. HUANG - Mentor Graphics, D. XIANG - Tsinghua University
Session 12B: Reducing Test & Diagnosis Costs
Moderator: J. Dworak - Southern Methodist U.
- Multi Domain Test: Novel Test Strategy to Reduce the Cost of Test
Y. TAKAHASHI, A. MAEDA - Verigy Japan K.K.
- Low-Cost Diagnostic Pattern Generation and Evaluation Procedures for Noise-Related Failures
J. MA - University of Connecticut, N. AHMED - Texas Instruments, M. TEHRANIPOOR - University of Connecticut
- Sigma-Delta Modulation Based Wafer-Level Testing for TFT-LCD Source Driver ICs
W.-A. LIN - National Taiwan University, C.-C. Li - Himax Technologies, J. L. HUANG - National Taiwan University
12:00pm-01:15pm Lunch
01:15pm-02:45pm Sessions 13
Special Session 13A: Embedded Tutorial: Practical Signal Processing at Mixed Signal Test Venues - Trend Removal, Noise Reduction, Wideband Signal Capturing -
Organizer: H. OKAWARA - Verigy Japan
Speaker: H. OKAWARA - Verigy Japan
Moderator: A. Chatterjee - Georgia Institute of Technology
Abstract: The presentation talks about topics about waveform sampling and frequency spectrum. Several fundamental topics are reviewed first. Then practical application examples are presented such as the trend removal and the noise reduction by FFT&IFFT, and the waveform capturing of a high-speed PRBS digital signal stream.
Session 13B: Hot Topic: Smart Silicon
Organizers: L. WINEMBERG - Freescale S., M. TEHRANIPOOR - U. Connecticut
Moderator: L. WINEMBERG - Freescale Semiconductor
Abstract: The goal of this Hot Topic Session is to discuss this cutting-edge topic that is being researched by several teams in both academia and industry, and debate which is the best approach for sub-65nm silicon designs. The point of debate will be what embedded circuits make the most sense (aging, enablement of more aggressive design, characterization, diagnosis, debug, etc.).
- Yin and Yang of Embedded Sensors for Post-Scaling-Era
A. GATTIKER - IBM Research Austin
- Accelerating ASIC Debug, Diagnostics and Quality
M. KAMM - Cisco
- Why is Access to Embedded Instrumentation so Critical Today
A. CROUCH - Asset-Intertech
Session 13C: Hot Topic: Design & Test of 3D and Emerging Memories
Organizer: C.-W. WU, National Tsing Hua University / ITRI
Moderator: L.C. Wang - U. of California at Santa Barbara
Abstract: Three talks that cover design of reliable, emerging memories, with emphasis on 3D memories, DRAM and non-volatile memories are included. Also a new class of memory, the Storage Class Memory (SCM), is intoruduced, and its reliability issues are discussed.
- 3D Memory Design
D. DUNNING - Intel
- New Design Considerations for 3D-Memories
F. CHEN - ITRI
- Making Storage-Class Memory Practical in Future Memory Hierarchy
H.-H. LEE - Georgia Institute of Technology
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