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Click HERE to download the PDF version of the program
(Tutorial 3 has been canceled)
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Apr 28th, 2008
9:00am - 10:30am Plenary Session
| Welcome message: | Alex Orailoglu, General Chair |
| Keynote Speaker: | Michael Campbell, Senior Vice President of Engineering, Qualcomm CDMA Technologies |
| Program Introduction: | Peter Maxwell and Cecila Metra, Program Co-Chairs |
| Invited Keynote: | "A Revolution in Design and Test Technology," Prof. Melvin Breuer, University of Southern California |
| Awards Presentation |
TTTC Most Successful Technical Meeting Award
TTTC Most Populous Technical Meeting Award
VTS 2007 Best Paper Award
VTS 2007 Best Panel Award
VTS 2007 Best Innovative Practices Award
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11:00am - 12:00pm Sessions 1
Session 1A: Testing for High Speed Communication Systems
Moderator: B. Courtois (TIMA)
- Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems
QINGQI DOU (University of Texas at Austin), Jacob ABRAHAM (University of Texas at Austin)
- Test Enabled Process Tuning for Adaptive Baseband OFDM Processor
Muhammad NISAR (Georgia Institute of Technology), Abhijit CHATTERJEE (Georgia Institute of Technology)
- Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links
Dongwoo HONG (University of California, Santa Barbara), KWANG-TING CHENG (University of California, Santa Barbara)
Session 1B: Compaction for Testing
Moderator: T. Williams (Synopsys)
- How Many Test Patterns are Useless?
Francois-Fabien FERHANI (Stanford University), Nirmal SAXENA (NVIDIA), Edward MCCLUSKEY (Stanford CRC), Phil NIGH (IBM)
- Constructing Augmented Multimode Compactors
Emil GIZDARSKI (Synopsys)
- Increasing Output Compaction in Presence of Unknowns using an X-Canceling MISR with Deterministic Fault Detection
Ritesh GARG (University of Texas at Austin), Richard PUTMAN (Cirrus Logic), Nur TOUBA (University of Texas at Austin)
IP Session 1C: Highways to Zero-defects: Industrial Approaches
| Organizer: | A. K. Majhi (NXP Semiconductors, Eindhoven, Netherlands) |
| Moderator: | D. Wu (Intel) |
| Description: |
Critical products like automotive, aerospace and medical demand 0-defect silicon. This Innovative Practices session will address
different approaches taken by some of the key semiconductor manufacturers to achieve zero-defects. The three presentations in this
session, and their descriptions are given below.
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| Presentations: |
DFT Opportunities to achieve Zero Defects
Rajesh Raina, LeRoy Winemberg (Freescale Semiconductors, USA)
Abstract...
Statistical Scan Diagnosis - new road to high quality
Stefan Eichenberger, Camelia Hora, Jeroen Geuzebroek, Bram Kruseman, Ananta K. Majhi (NXP Semiconductors, Netherlands)
Abstract...
Extending Quality Beyond Time Zero Through Additional DFT and Test
Srinivas Kumar Vooka, Vinay Jayaram and Rubin Parekhji (Texas Instruments, Inc.)
Abstract...
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1:20pm - 2:20pm Sessions 2
Session 2A: ATE Data Volume and False/Acceptable Test Fails
Moderator: E. Volkerink (Verigy)
- Inconsistent Fails due to Limited Tester Timing Accuracy
Intaik PARK (Stanford University), Donghwi LEE (Stanford University), Erik CHMELAR (LSI Logic), Edward MCCLUSKEY (Stanford CRC)
- A Regression Based Technique for ATE-aware Test Data Volume Estimation of System-on-Chips (SoCs)
Srivaths RAVI (Texas Instruments India), Rajesh TIWARI (Texas Instruments India), Abhijeet SHRIVASTAVA (Texas Instruments India), Mahit WARHADPANDE (Texas Instruments India), Rubin PAREKHJI (Texas Instruments India)
- Basing acceptable error-tolerant performance on significance-based error-rate (SBER)
Zhaoliang PAN (University of Southern California), Melvin BREUER (University of Southern California)
Session 2B: Test and Diagnosis of Scan Chains
Moderator: B. Cory (Nvidia)
- Diagnosis of Scan Clock Failures
NADIR BASTURKMEN (Intel Corporation), King Leong LEE (Intel Corporation), Srikanth VENKATARAMAN (Intel Corporation)
- An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation
SUNGHOON CHUN (Yonsei University), Yongjoon KIM (Yonsei University), Taejim KIM (Yonsei University), Sungho KANG (Yonsei University)
- On the Detectability of Scan Chain Internal Faults - An Industrial Case Study
Fan YANG (University of Iowa), Sreejit CHAKRAVARTY (LSI Logic), Narendra DEVTA-PRASANNA (LSI Logic), Sudhakar REDDY (University of Iowa), Irith POMERANZ (Purdue University)
IP Session 2C: Device Degradation and Infant Mortality
| Organizer: | J. W. Tschanz (Intel Corporation) |
| Moderator: | G. Eide (Magma) |
| Description: |
In an era of increasing performance targets and ever more stringent power requirements, design margins are shrinking more than ever.
It is therefore critical to be able to understand the factors which impact product reliability and to accurately predict their effects.
Overestimate the impact of NBTI, HCI, and TDDB on the product, and critical performance or power is left on the table.
Underestimate these effects and the product suffers an unacceptable failure rate. Further complicating this picture is the fact that the
relative importance of these different degradation mechanisms can change drastically from one process generation to the next.
The three presentations in this session show how a combination of careful modeling combined with product measurement data is used to set the
reliability guardbands that are used. The speakers will demonstrate their unique approaches towards reliability modeling and characterization,
and give insight into the reliability testing and characterization challenges that lie ahead.
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| Presentations: |
Realistic Projections of Product Fmax and Vmin Shifts due to HCI, NBTI, and TDDB
Amr Haggag (Freescale)
Comprehending NBTI at the Product Level
Vijay Reddy (Texas Instruments)
In-line Manufacturing Measurement of Infant Mortality Thermal Activation Energy
Arman Vassighi (Intel Corporation)
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2:40pm - 3:40pm Sessions 3
Session 3A: Memory Diagnosis and Repair
Moderator: M. Rodgers
- An SRAM Design-for-Diagnosis Solution based on Write Driver Voltage Sensing
Alexandre NEY (LIRMM), Patrick GIRARD (LIRMM), Serge PRAVOSSOUDOVITCH (LIRMM), Arnaud VIRAZEL (LIRMM), Magali BASTIAN (Infineon), Vincent GOUIN (Infineon)
- An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-operation Dynamic Faults in Random Access Memories
Gurgen HARUTYUNYAN (Virage Logic), Valery VARDANIAN (Virage Logic)
- Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry
NILADRI MOJUMDER (Purdue University), Saibal MUKHOPADHYAY (Georgia Institute of Technology), JAE-JOON KIM (IBM T.J. Watson Research Center), Ching-Te CHUANG (IBM T.J. Watson Research Center), Kaushik ROY (Purdue University)
Session 3B: New Topic: Why Nanoscale Physics Favors Quantum Information & Why Computing is Possible in Spite of Quantum Uncertainty
| Organizers: | Igor L. Markov and John P. Hayes (University of Michigan, USA) |
| Moderator: | B. Kaminska (Simon Fraser Univ.) |
| Description: |
As transistor dimensions approach atomic scale, quantum-mechanical effects such as tunneling and spin become important ingredients in accurate
performance models of integrated circuits. Read more...
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IP Session 3C: Automatic Test Development for Mixed-Signal/RF Circuits
| Organizer: | V. Zivkovic
(NXP Semiconductors, the Netherlands) |
| Moderator: | K. Arabi (Qualcomm) |
| Presenters: |
ATPG for SerDes Testing on any ATE, Bench-Top, or Simulator
Stephen Sunter, Aubin Roy (LogicVision, Canada), Givargis Danialy (LogicVision, USA)
Abstract...
Test Verification and Program Generation for Modular System-on-Chips with Mixed-Signal Cores
V. Zivkovic, Rene Jonker (NXP, the Netherlands)
Abstract...
Automating Test Development for Mixed-Signal and RF circuits - Can Current Test Help?
Hans Manhaeve (Q-Star Test, Belgium)
Abstract...
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4:00pm - 5:00pm Sessions 4
Session 4A: Modeling and Testing for Nanometer CMOS
Moderator: S. Venkataraman (Intel)
- Gate Oxide Early Life Failure Prediction
Tze Wee CHEN (Stanford University), Kyunglok KIM (Stanford University), Young Moon KIM (Stanford University), Subhasish MITRA (Stanford University)
- Full Open Defects Under Tunnelling Leakage Current in Nanometric CMOS
Daniel ARUMI DELGADO (Universitat Politecnica de Catalunya), Rosa RODRIGUEZ-MONTANES (Universitat Politenica de Catalunya), Joan FIGUERAS (Universitat Politècnica de Catalunya), Stefan EICHENBERGER (NXP), Camelia HORA (NXP), Bram KRUSEMAN (NXP)
- Signature Rollback - A Technique for Testing Robust Circuits
Uranmandakh AMGALAN (University of Paderborn), Christian HACHMANN (University of Paderborn), Sybille HELLEBRAND (University of Paderborn), Hans-Joachim WUNDERLICH (Universität Stuttgart)
Session 4B: Low Power Scan Testing
Moderator: C. Landrault (LIRMM)
- Bounded Adjacent Fill for Low Capture Power Scan Testing
Anshuman CHANDRA (Synopsys Inc.), Rohit KAPUR (Synopsys Inc.)
- Reducing Scan Shift Power at RTL
Elif ALPASLAN (Brown University), Yu HUANG (Mentor Graphics Co.), Xijiang LIN (Mentor Graphics Corp.), Wu-Tung CHENG (Mentor Graphics Corporation), JENNIFER DWORAK (Brown University)
- Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes
Yu-Ze Wu (National Chiao Tung University), Mango Chia-Tso Chao (National Chiao Tung University)
IP Session 4C: Bridging Pre-Silicon Verification and Post-Silicon Validation and Debug
| Organizers: | E. J. Marinissen, NXP Semiconductors (erik.jan.marinissen@nxp.com) |
| Moderator: | N. Nicolici (McMaster Univ.) |
| Description: |
In this session, we discuss how to bridge the pre-silicon verification to post-silicon validation and debug.
Can test patterns and test benches developed for verification be reused during validation? Can bugs identified in
validation be confirmed again in the verification environment? How can the DfT infrastructure available on-chip for
manufacturing test help with bridging pre-silicon verification and post-silicon validation and debug? Are the scan
chains sufficient or do we need more on-chip support? Are there any other established test technologies that can aid
the post-silicon validation process?
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| Presentations: |
Pre-Silicon Verification Perspective
Gil Shurek and Allon Adir (IBM Research Division, Haifa Research Laboratory, Israel)
Abstract...
Post-Silicon Design-for-Debug Perspective
Miron Abramovici and Paul Bradley (DAFCA Inc., USA)
Abstract...
Post-Silicon Hardware/Software Co-Debug Perspective
Bart Vermeulen and Kees Goossens (NXP Semiconductors, The Netherlands)
Abstract...
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8:00pm - 9:30pm SESSIONS 5
Special Session 5A: Embedded Tutorial - Robust Design: Techniques and Trends
| Organizer: | M. Zhang (Intel) |
| Moderator: | Z. Navabi (Worcester Poly) |
| Description: |
Relentless technology scaling presents a challenging task of designing reliable systems in the presence of transient, intermittent, and gradual errors. It is crucial for the design & test community to understand the origin and impact of these errors, methods to characterize, screen, and analyze them, as well as design techniques to mitigate them. In this session, the speakers will provide comprehensive reviews of these three aspects of the robust design challenges with different industry/academia perspectives. Discussion on error sources will focus on soft errors, process variation, and device degradation. Both theoretical modeling of these effects and experimental data from test chips will be presented. We will focus on logic and memory circuits for the design techniques to demonstrate the principles of robust design. A full-chip deployment strategy of such robust circuit elements will also be discussed. Experimental data and theoretical projection on sub-65nm technologies will be presented to illustrate the trend and potential new challenges for future technologies and motivate future robust design research.
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| Presenters: |
Kaushik Roy (Purdue University)
Kanak Agarwal (IBM)
Ming Zhang (Intel)
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Special Session 5B: Apprentice - VTS Edition
| Organizer: | K.S. Kim (Intel) |
| Moderator: | K.S. Kim (Intel) |
| Description: |
The main objective of this active "panel" is to increase technical interaction among attendees. Team leaders listed below will recruit participants
to their team. Each team will try to clearly articulate the problems and come up with proposals to solve this problem. These teams will present their
findings and business proposals in front of judges later during the conference. The winning team will be announced during the social event.
Read more...
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| Presenters: |
A. Crouch (Verigy)
J. Dastidar (Altera)
A. Gattiker (IBM)
R. Kapur (Synopsys)
S. Ozev (Duke Univ.)
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Special Session 5C: Student Posters
| Organizers: | J. Plusquellic (UMBC) |
Apr 29th, 2008
8:30am - 9:30am Sessions 6
Session 6A: Testing of Analog Circuits
Moderator: J. M. Cooper (Intel)
- A Time-Domain Method for Pseudo-Spectral Characterization
APURVA MISHRA (University of Washington), Mani SOMA (University of Washington)
- A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays
Chen-Wei LIN (National Taiwan University), Jiun Lang HUANG (National Taiwan University)
- Fast Accurate Tests for Multi-Carrier Transceiver Specifications: Phase Noise and EVM
Rajarajan SENGUTTUVAN (Georgia Institute of Technology), Abhijit CHATTERJEE (Georgia Institute of Technology), Soumendu BHATTACHARYA (Georgia Institute of Technology)
Session 6B: ATPG I
Moderator: L. Miclea (U Tech of Cluj)
- Automatic Test Pattern Generation for Interconnect Open Defects
Stefan SPINNER (Albert Ludwigs University of Freiburg), Ilia POLIAN (Albert Ludwigs University of Freiburg), Piet ENGELKE (Albert Ludwigs University of Freiburg), Bernd BECKER (Albert Ludwigs University of Freiburg), Martin KEIM (Mentor Grpahics Corp.), Wu-Tung CHENG (Mentor Graphics Corporation)
- On the Relaxation of N-detect Test Sets
STELIOS N NEOPHYTOU (University of Cyprus), Maria MICHAEL (University of Cyprus)
- Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
SUDARSHAN BAHUKUDUMBI (Duke University), Krishnendu CHAKRABARTY (Duke University)
IP Session 6C: Post-Silicon Validation: Current Practices and New Challenges
| Organizer: | S. Gupta (University of Southern California) |
| Moderator: | M. Hunt (Qualcomm) |
| Description: |
In most existing flows for custom or semi-custom design, the quality of chips shipped to customers is ensured via a
sequence of three processes, namely pre-silicon verification of a chip’s design, post-silicon validation of the
first-silicon for the design (i.e., the first set of chips fabricated for the design), and testing of each fabricated
copy when the design is fabricated in high volume. While verification and testing have been active areas of research,
post-silicon validation has developed primarily via intensive engineering practice. However, a noticeable trend has
emerged in recent years: Despite advances in design and verification, for high-performance designs it is becoming
increasingly common for many causes of circuit misbehavior that can cause significant yield loss to be first discovered
during post-silicon validation. This presents numerous challenges, many of interest to the testing community
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In this session, validation experts from three leading companies will share their insights. First, they will describe
their validation methodologies and some recent case studies. Second, they will present emerging challenges, especially
those the testing community may be able to address, e.g., development of new approaches to estimate and enhance quality
of validation and new techniques to identify root causes behind erroneous behaviors exposed during validation.
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| Presentations: |
Post-silicon validation challenges of highly integrated processors
Priyadarsan Patra and Chinna Prudvi (Intel Corporation)
A bug's life... and how the test research community can shorten it
Ishwar Parulkar (Sun Microsystems)
Optimizing ATPG scan stimulus for post-silicon validation debug with diagnostic equipment
John West, John Drummond, Craig Bullock, and Chuck Pilch (Texas Instruments)
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9:50am - 10:50am Sessions 7
Session 7A: Testing of RF Circuits
Moderator: M. Sawan (Ecole Poly de Montreal)
- Low Cost RF Receiver Parameter Measurement with On-chip Amplitude Detectors
CHAOMING ZHANG (University of Texas at Austin), Ranjit GHARPUREY (University of Texas at Austin), Jacob ABRAHAM (University of Texas at Austin)
- An Integrated BiST Solution for Characterizing RF Transceivers through a Single Measurement
ERDEM ERDOGAN (Duke University), Sule OZEV (Duke University)
- ACT: Adaptive calibration test based performance improvement and test enhancement of wireless RF front ends
VISHWANATH NATARAJAN (Georgia Institute of Technology), Rajarajan SENGUTTUVAN (Georgia Institute of Technology), Shreyas SEN (Georgia Institute of Technology), Abhijit CHATTERJEE (Georgia Institute of Technology)
Session 7B: Testing of Transition Faults and Small Delay Defects
Moderator: N. Touba (Univ. of Texas at Austin)
- Synthesis for Broadside Testability of Transition Faults
Irith POMERANZ (Purdue University), Sudhakar REDDY (University of Iowa)
- LSTDF: Low-Switching Transition Delay Fault Pattern Generation
Mohammad TEHRANIPOOR (University of Connecticut), Jeremy LEE (University of Connecticut)
- Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Mahmut YILMAZ (Duke University), Krishnendu CHAKRABARTY (Duke University), Mohammad TEHRANIPOOR (University of Connecticut)
IP Session 7C: Design for Yield and Manufacturability
| Organizer: | S. Shoukourian (Virage Logic) |
| Moderator: | S. Taneja (Cadence) |
| Description: |
Increased manufacturing variability in leading-edge process technologies requires new paradigms and solution technologies for
yield optimization. SoC manufacturability and yield entails design-specific optimization of the manufacturing, and thus
enhanced communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and
Design-for-Yield (DFY) methodologies and tools have been proposed in recent years. Some of these tools are leveraged during
back-end design, others are applied post-GDSII, and still others are applied post-design, from reticle enhancement and
lithography through wafer sort, packaging, final test and failure analysis. DFY and DFM can dramatically impact the business
performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFY and DFM solutions
is an investment, and choosing the most cost effective one(s) requires careful analysis of integration and schedule overheads,
versus quantified benefits. This session analyzes the key trend and challenges, and provides a set of innovative DFM and
DFY practices used for today’s SoC designs.
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| Presenters: |
Performance Binning in the Presence of Process Variability
A. Majumdar, V. Ganti (AMD)
Yield Acceleration based on Design for Yield and Manufacturability
Yervant Zorian (Virage Logic)
A Realistic View of DFM or Search for the Holy Grail
Manuel d’Abreu (SanDisk)
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11:10am - 12:10pm Sessions 8
Session 8A: Delay Test and Measurement
Moderator: V. Agrawal (Auburn Univ.)
- Dynamic Compaction for High Quality Delay Test
Zheng WANG (Texas A&M University), Duncan WALKER (Texas A&M University)
- An All-Digital High-Precision Built-In Delay Time Measurement Circuit
Ming-Chien TSAI (Feng-Chia University), CHING-HWA CHENG (Feng-Chia University)
- Error Sequence Analysis
Jaekwang LEE (Stanford University), Intaik PARK (Stanford University), Edward MCCLUSKEY (Stanford University)
Session 8B: Testing and Error Tolerance for Emergent Technology Circuits
Moderator: R. Makki (UAE Univ.)
- QBIST: 1-Testable Quantum Built-In Self-Test for any Boolean Circuit
Yao-Hsin CHOU (National Taiwan University), I-Ming TSAI (National Taiwan University), Sy Yen KUO (National Taiwan University)
- A Statistical Approach to Characterizing and Testing Functionalized Nanowires
James DARDIG (Yale University), Haralampos STRATIGOPOULOS (TIMA), Eric STERN (Yale University), Mark REED (Yale University), Yiorgos MAKRIS (Yale University)
- A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-assemblies
MASOUD HASHEMPOUR (Northeastern University), Zahra MASHREGHIAN ARANI (Northeastern University), Fabrizio LOMBARDI (Northeastern University)
IP Session 8C: STIL Utilization in Practice
| Organizer: | K. Hatayama (STARC) |
| Moderator: | P. Mantri (Sun Microsystems) |
| Description: |
Standardization of test-related information, not only test data but also testing environmental information, is key for
realizing totally standardized test environment from design to diagnosis. On this point, STIL, Standard Test Interface
Language (IEEE 1450.x series, see table below) can have an important role.
Read more...
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| Presentations: |
Building Standard Test Environment based on STIL
Hirofumi Kamitokusari, Takashi Aikyo (STARC)
A STIL-based Desktop ATPG Diagnostic Environment
Givargis Danialy, Stephen Pateras (LogicVision)
STILAccess: Shared Libraries for STIL Parser
Hiroshi Date (System JD)
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1:45pm - 3:15pm Sessions 9
Special Session 9A: Hot Topic: Memory BIST: Yield Management and DPPM Reduction
| Organizers: | P. Ehlig, A. Kokrady (Texas Instruments) |
| Moderator: | T. M. Mak (Intel) |
| Description: |
With shrinking technology, it is getting harder to manufacture and test memories which today occupy more than 50%-60% of chip area and dominate the defects and customer returns in today’s integrated circuits. Previously unheard of fault/defect types are causing designs to fail reducing yield and increasing Defective Parts per Million (DPPM). It is important for the design & test community to understand the need to screen and analyze the defects and find out techniques to mitigate them. In this session, we explore various ways of reducing the impact on yield and DPPM.
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| Presentations: |
Memory Yield Improvement through Multiple Test Sequences and Application-aware Fault Models
Aman Kokrady, C.P. Ravikumar (Texas Instruments), Nitin Chandrachoodan (IIT Madras)
Abstract...
Lithography and Memories: From Shapes to Electrical
Puneet Gupta (UCLA, USA), Clive Wu (Aprio Technologies)
Abstract...
Panel Discussion: Yield Management and DPPM Reduction for sub micron memories
Peter Ehlig (Texas Instruments), Yervant Zorian (Virage Logic), Rob Aitken (ARM)
Abstract...
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Session 9B: Embedded Tutorial Nanoelectronics - what next? From Moore's Law to Feynman's Vision
| Organizers: | S. Mourad (Santa Clara Univ.) and Y. Zorian (Virage Logic) |
| Moderator: | S. Mourad (Santa Clara Univ.) |
| Description: |
The limit of present silicon transistors is set by the manufacturing process and not by the laws of physics. Emerging nanomaterials has provided new possibilities for higher packing density, higher carrier mobilities, and higher/lower dielectric constants. Although nanotechnology is usually defined as utilizing technology with less than 100nm in the minimum feature size, nanoelectronics often refer to devices that are so small that inter-atomic interaction, ballistic transport, and quantum mechanical properties need to be studied. These phenomena are expected to assume much more prominent roles in silicon-based devices fabricated using sub-45 nm technologies.
Nanoelectronic devices such as Single Electron Transistor, Resonant Tunnel Diodes and Quantum Dot Arrays are still under development as practical circuitry, but they do hold a great promise. This is also true of molecular devices that can self-assemble to form a large system. One of the best known families of nanomaterials is carbon nanostructures such as nanotube, nanofiber, and graphene. They hold great promise as candidates for ultra-fast switches as well as interconnect and thermal interface materials. In this session, three speakers will present different facets of nanoelectronics to prepare us test engineers for the challenges integrated circuit technology faces now and in the near future.
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| Presentations: |
One Dimensional Nanostructures and their Applications
M. Meyyappan (NASA Ames Research Center, Moffett Field)
Abstract...
Emerging Nanoelectronic Devices
Bin Yu (UARC/NASA Ames Research Center, Moffett Field)
Abstract...
Carbon Nanostructures as On-chip Interconnects
Cary Yang (Center of Nanostructures, Santa Clara University, USA)
Abstract...
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Session 9C: TTTC 2008 Best Doctoral Thesis Contest
| Organizer: | Y. Makris (Yale University) |
| Moderator: | H. Stratigopoulos (TIMA Laboratory) |
| Description: |
This session is the final round of the TTTC 2008 Best Doctoral Thesis Contest. This contest is organized by the TTTC Student Activities Committee for the fourth consecutive year and aims to promote and strengthen the interaction between graduate students and the industrial community, as well as to serve as a process by which student work is exposed to and tested under real-life industrial needs. This is achieved by offering students the chance to present their work in a conference environment to academic and industrial test experts, who will evaluate and comment in terms of novelty and advancement of industrial practice.
In the preliminary round of this contest, doctoral students who are expected to graduate in 2008 were invited to submit a one page abstract of their thesis, where they defined the problem and its relevance to industry, described existing industrial practices for solving the problem and explained the proposed methodology and how it advances the theory and/or practice in the particular field. The abstracts were reviewed by a panel of industrial and academic experts and a set of finalists were selected for the final round of the contest.
In this final round, during a dedicated session at the IEEE VLSI Test Symposium (VTS’08), each contestant is given a ten minute slot in front of a panel of experts, split equally between oral presentation and Q&A period. The panel of experts will judge the presented doctoral theses with regards to theoretical advancement, industrial relevance and presentation, and the winner of the contest will receive the 2008 TTTC Doctoral Thesis Award during the social event of the Symposium, to which all finalists are invited. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine.
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| Judges: |
M. Abadir (Freescale)
T. M. Mak (Intel)
T. McLaurin (ARM)
J. Rajski (Mentor Graphic)
J. Saxena (Texas Instruments)
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| Contestants: |
Sudarshan Bahukudumbi (Duke University - USA), Giuseppe Di Guglielmo (Universita di Verona - Italy),
Francois-Fabien Ferhani (Stanford University - USA), Michelangelo Grosso (Politecnico di Torino - Italy),
Gurgen Harutyunyan (Yerevan State University - Armenia), Naghmeh Karimi (University of Tehran - Iran),
Ritesh Turakhia (Portland State University - USA),
Devanathan Varadarajan (Indian Institute of Technology Madras, India)
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3:30pm - 11:00pm Social Program
Apr 30th, 2008
9:00am - 10:00am Sessions 10
Session 10A: Testing of Mixed Signal Circuits
Moderator: I. Hartanto (Xilinx)
- Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits
Byoungho KIM (University of Texas at Austin), Nash KHOUZAM (National Semiconductor), Jacob ABRAHAM (University of Texas at Austin)
- Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data
Sounil BISWAS (Carnegie Mellon University), Ronald Shawn BLANTON (Carnegie Mellon University)
- Parallel Loopback Test of Mixed-Signal Circuits
Joonsung PARK (University of Texas at Austin), HONGJOONG SHIN (University of Texas at Austin), Jacob ABRAHAM (University of Texas at Austin)
Session 10B: ATPG II
Moderator: H. Konuk (Broadcom)
- Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests
Irith POMERANZ (Purdue University), Sudhakar REDDY (University of Iowa)
- An ATPG Methodology to Detect Weight Related Defects in Threshold Logic Gates
MANOJ KUMAR GOPARAJU (Southern Illinois University), Spyros TRAGOUDAS (Southern Illinois University)
- Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults
Sethuram RAJAMANI (Qualcomm), Michael BUSHNELL (Rutgers), Vishwani AGRAWAL (Auburn University)
IP Session 10C: Testing for Complex Failure Mechanisms and Process Variations of Memories
| Organizer: | M Azimane (NXP Semiconductors) |
| Moderator: | B. Wang (AMD) |
| Description: |
Memory area on current designs in the 90nm, 65nm and 45nm designs is increasing exponentially given the nature of applications
and the drive to embed entire systems on a single chip. With ever increasing process complexity and shrinking technologies,
different defect types that manifest themselves as complex failure mechanisms and process variations on memories are also
increasing proportionally. Traditional memory test techniques like functional vectors are no longer sufficient. In the mean
time, new DFT methods and Built-in Self-Test (BIST) approaches are evolving to test for these defects and garner enough data
to increase memory test efficiency.
In the first presentation, Azimane et al. from NXP Semiconductors will focus on additional DFTs that could be implemented
in addition to BIST test algorithms to catch complex failure mechanisms and worst case process variations. They show that
the fault coverage of conventional march tests have reached saturation phase and time has come to jump to new test methods.
In the second presentation, and in cooperation between LIRMM and Infineon, Dilillo et al. have analyzed the impact of
technology scaling on defects and parameter deviations in embedded SRAMs. They showed how the impact of manufacturing
defects may vary with the level of integration (130 nm down to 45 nm) of eSRAMs core-cell belonging to the same family.
Secondly, they illustrate the effects of technology scaling (130 nm down to 45 nm) on device parameter variations.
In the third presentation, Jayaram et al. from Texas Instrument will address the pros/cons of BIST techniques and show how
programmable BIST offers almost unlimited flexibility on screening known and unknown defects in the presence of process
variation. In addition, they will offer some case-studies on hard-to-screen defects and present some implementation-level
details of programmable BIST on today’s complex designs. They will also address the aspect of designing memories to make test
easier and highlight some features that are critical in enabling efficient debug. Finally, they will cover some aspects of
hard vs. soft repair and external vs. Built-in Self-Repair (BISR).
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| Presentations: |
Dealing with complex failure mechanisms for high quality testing in Embedded SRAMs
Mohamed Azimane, Bram Kruseman, Stefan Eichenberger (NXP Semiconductors)
Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMs
L. Dilillo, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel (LIRMM, France), M. Bastian, V. Gouin (Infineon, France)
Flexible memory test architectures for combating subtle defects and process variations
Vinay Jayaram and Sherry Lai (Texas Instruments)
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10:20am - 11:20am Sessions 11
Session 11A: Debug and Diagnosis
Moderator: M. Michael (Univ. of Cyprus)
- Fast Measurement of the "Non-deterministic Zone" in Microprocessor Debug using Maximum Likelihood Estimation
DESTA TADESSE (Brown University), Joel GRODSTEIN (Intel Corporation), Ruth BAHAR (Brown University)
- Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
Joon-Sung YANG (University of Texas at Austin), Nur TOUBA (University of Texas at Austin)
- A General Failure Candidate Ranking Framework
ChiaChih YEN (Springsoft Inc.), Kai YANG (Novas), Yu-Chin HSU (Novas), Tayung LIU (Novas), ShenTien LIN (Springsoft), Henming LIN (Springsoft)
Special Session 11B: Embedded Tutorial: Measuring IC Timing Parameters - from Nano to Picoseconds
| Organizer: | S. Sunter (LogicVision) |
| Presenter: | S. Sunter (LogicVision) |
| Abstract: |
As CMOS IC dimensions scale below 90 nm, delays-of-interest range from nanoseconds to picoseconds. This increases the need for greater time measurement accuracy but off-chip (ATE-based) delay measurement techniques are becoming severely limited by fundamental properties of signal access paths off-chip and on-chip, such as noise, wire length, and impedance variation. On-chip measurement techniques have been proposed by IC designers, DFT engineers, and test engineers, with claimed accuracies ranging from nanoseconds to femtoseconds, at least in simulation.
This tutorial will survey most of the papers that provide silicon results published in the last 10 years, in both design and test journals/conferences, and some representative papers that include only simulated results, to discover the most promising directions for measuring and production testing today’s and future delays-of-interest. Delay parameters include instantaneous delay, average delay, and delay variation (long and short term, including jitter) in digital, analog, and wire paths, and they typically depend on voltage, frequency, and conditions. The measurement techniques will be categorized by suitability for measurement of one-shot and periodic events, then by measurement principle, and lastly by circuit technique and reported real-silicon capabilities.
The goal is to identify principles and techniques suitable for production testing (quick and process tolerant, using insignificant silicon area) and for IC characterization and debug too (flexible to handle unanticipated delays and accuracy).
Some of the conclusions are: isolation between engineers in different disciplines (design, DFT, test) results in sub-optimal solutions; simulations can be enhanced to include many deleterious effect but real silicon provides surprises when it comes to picoseconds; progress in the last 10 years has not tracked technology scaling because of discipline isolation and emphasis on simulation; a new standard test pin type might accelerate progress towards meeting production test requirements.
The intended audience is DFT and test engineers, and researchers.
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IP Session 11C: New Emerging Practices for Semiconductor Test
| Organizer: | P. Roddy (Advantest) |
| Moderator: | D. Appello (ST Microelectronics) |
| Description: |
This session will focus on practical applications for the semiconductor test process. The rapidly expanding development of
new semiconductor products is putting a strain on the industry's test resources. Several of the ITC 2007 speakers highlighted
the additional effort that will be required in the test area, to keep up with all the new designs. This session will explore
new and innovative test applications that are being used to address these challenges.
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| Presentations: |
Development of Common Tools & Tester Language for ATE, Rich Anderson, TSSI
Pete Decher (TSSI)
New RF Testing Innovations
Keith Schaub (Advantest America Inc.)
Migration of PXI Instruments into Semiconductor Production Test
Eric Starkloff, National Instruments
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11:40am - 12:40pm Sessions 12
Session 12A: Fault Tolerance
Moderator: F. Lombardi (Northeastern Univ.)
- Algorithm Level Fault Tolerance: a New Technique to Cope with Radiation Induced Faults in Matrix Multiplication Algorithms
Carlos LISBOA (Universidade Federal do Rio Grande do Sul), COSTAS ARGYRIDES (Bristol University), Dhiraj PRADHAN (Bristol University), Luigi CARRO (Universidade Federal do Rio Grande do Sul)
- Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects
Ying ZHANG (Chinese Academy of Sciences), HUAWEI LI (Chinese Academy of Sciences), Xiaowei LI (Chinese Academy of Sciences), Yu HU (Institute of Computing Technology)
- Low Cost Highly Robust Hardened Storage Cells Using Blocking Feedback Transistors
Michael NICOLAIDIS (TIMA Laboratory), Dan ALEXANDRESCU (Iroc tech.), Renaud PEREZ (Iroc Tech.)
Session 12B: Testing of Path Delay Faults
Moderator: C. Aktouf (Defacto)
- Multiple Coupling Effects Oriented Path Delay Test Generation
MINJIN ZHANG (Institute of Computing Technology, Chinese Academy of Sciences), HUAWEI LI (Chinese Academy of Sciences), Xiaowei LI (Chinese Academy of Sciences)
- A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm
Michelangelo GROSSO (Politecnico di Torino), Paolo BERNARDI (Politecnico di Torino), Ernesto SANCHEZ (Politecnico di Torino), Matteo SONZA REORDA (Politecnico Di Torino), Kyriakos CHRISTOU (University of Cyprus), Maria MICHAEL (University of Cyprus)
- An Industrial Case Study of Sticky Path-Delay Faults
Ide HUANG (USC), Yi-Shing CHANG (Intel), Sandeep GUPTA (University of Southern California), Sreejit CHAKRAVARTY (LSI)
IP Session 12C: Fault Localization Practices and Challenges
| Organizer: | S. Tammali (Texas Instruments, India) |
| Moderator: | B. Eklow (Cisco) |
| Presentations: |
Current practices of FA Engineer / DFT engineer and Challenges
Sarveswara Tammali (Texas Instruments, Bangalore), Kendal Scott Wills and David Paul (Texas Instruments, USA)
Abstract...
Principle and Practice of Modern Scan Diagnostics
Scott Cook and Brady Benware (Mentor Graphics)
Abstract...
Tester-based Scanning Optical Microscope Techniques for Fault Localization
Jacob CH Phang (SEMICAPS Pte Ltd) and MR Bruce (AMD Inc)
Abstract...
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2:00pm - 3:30pm Sessions 13
Special 13A: Panel: Mitigating Reliability, Yield and Power Issues in Nano-CMOS: Design Problem or EDA Problem?
| Organizer: | M. Nicolaidis (TIMA) |
| Moderator: | Y. Zorian (Virage Logic) |
| Co-Organized: |  |
| Description: |
Silicon based CMOS technologies are fast approaching their manufacturability limits. In newer processes, power dissipation, fabrication yield, and
reliability are steadily worsening, making further nanometric scaling increasingly difficult. In particular, yield as well as reliability are threatened
by issues such as manufacturing process variations, on-chip voltage and temperature variability, accelerated aging and wearout, radiation induced
soft-errors and cross talk.
Read more...
|
| Panelists: |
Shaleen Bhabhu (Cadence)
Rubin A. Parekhji (Texas Instruments)
Michael Nicolaidis (TIMA)
Ming Y. Zhang (Intel)
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Session 13B: Hot Topic: Biomedical Devices - New Test Challenges
| Organizer: | B. Kaminska (Simon Fraser University, Canada) |
| Moderator: | K. Eshraghian (Univ. of Cal.) |
| Presentations: |
Massively parallel wireless sensing from the cortex: Design and test challenges
Mohamad Sawan, Ecole Polytechnique, Montreal, Canada
Abstract...
Design and Calibration of EEG Electrode Arrays for Wearable BCI
Gert Cauwenberghs, University of California, San Diego
Abstract...
Testing of Digital Microfluidic Biochips: Fault Models, Test and Fault Diagnosis
Krishnendu Chakrabarty, Duke University, North Carolina
Abstract...
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Session 13C: Panel: Is Ubiquitous RF at Odds with Test?
| Organizer: | Ajay Khoche |
| Moderator: | Abhijit Chatterjee (Georgia Inst. of Tech.) |
| Description: |
The drive for using RF to provide universal connectivity is forcing various wireless standards being supported in a single device. Moreover this functionality is expected in consumer devices where the cost pressure is significant. The cost pressure coupled with the everlasting quest for miniaturization leads to many of these wireless interfaces being added to a single chip or a package. The instrumentation required for testing an RF interface is traditionally more expensive than the digital, memory or mixed signal components. The proliferation of RF interfaces on a chip/package would push the test cost even higher and could potentially become a bottleneck in enabling such ubiquitous RF devices. This panel will discuss state of RF test technology with respect to the needs of such ubiquitous RF devices to identify the gaps, if any.
|
| Panelists: |
Octavio Martinez (Qualcomm)
Greg McCarter (Verigy)
Ken Harvey (Teradyne)
Keith Schaub (Advantest)
Paul Berndt (Cypress Semiconductor)
Mark Berry (Amkor)
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