All sessions are scheduled according to the local time.

Room names:
Room 1 = Merlot & Syrah (100 people)
Room 2 = Cabernet (50 people)
Room 3 = Zinfandel (50 people)

 

Monday, April 27, 2026

7:30 AM – 8:30 AM Registration

Grand Foyer

8:30 AM – 9:00 AM Plenary Session – Welcome by the Chairs & Awards

Grand Ballroom

9:00 AM – 10:00 AM Opening Keynote

Grand Ballroom

10:00 AM – 10:30 AM Break

10:30 AM – 11:30 AM Regular Session 1: “Machine Learning for Test and Security”

Room 1 (Merlot & Syrah)

A Physics-Informed Machine Learning Framework for Electromigration Time-to-Failure Prediction
Saeid KARIMPOUR, Emmanuel NTI DARKO, Kelvin TAMAKLOE, Degang CHEN (Iowa State University)

WaferIntel: A Lightweight, SME-Driven Framework for Advanced Defect Pattern Analysis
Dmitri KALASHNIKOV, Jianqiao HUANG, Yan PAN (Microsoft)

WALET: SHAP-Guided Classification of Wafer-Level E-Test Variability for Early Process Risk Detection
Ching-Yi CHANG (UT Dallas), Matthew NIGH (UC San Diego), John CARULLI (Advantest), Yiorgos MAKRIS (UC San Diego)

10:30 AM – 11:30 AM Special Session 1: “Hardware Acceleration for Zero-Knowledge Proof: Recent Advances and Challenges”

Room 2 (Cabernet)

Organizer: Jiafeng Xi
Chair: TBD

Hardware Acceleration Methodologies for Zero-Knowledge Proof: Existing Challenges and Further Innovations
Jiafeng Xi (Villanova University)

Applying Winograd BFU for Implementing NTT with Large Degree and Large Modulus
Debapriya Basu Roy (IIT Kharagpur, India)

Hardware Acceleration Challenges for Quantum-Secure Zero-Knowledge Proofs: A Balanced Design Perspective
Pengzhou He (Auburn University at Montgomery)

10:30 AM – 11:30 AM IP Session 1: “Multi-dies Interconnect Test”

Room 3 (Zinfandel)

Organizer: Tapan Chakraborty
Chair: TBD

Efficient Multi-die test architecture & repair Methods
Tapan Chakraborty (Renesas Electronics)

11:30 AM – 12:30 PM Regular Session 2: “Generative AI for Test, Verification and Security”

Room 1 (Merlot & Syrah)

DefectVICL: Data-Efficient Wafer Defect Classification with Vision In Context Learning
Md Fahim UL ISLAM, Soyed Tuhin AHMED (Arizona State University), John CARULLI (Advantest), Krishnendu CHAKRABARTY (Arizona State University)

FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
Jiaxin WAN (University of Illinois, Champaign-Urbana), Chia-tung HO, Yunsheng BAI (NVIDIA), Cunxi YU (University of Maryland, College Park), Deming CHEN (University of Illinois, Champaign-Urbana), Haoxing REN (NVIDIA)

RTL-Forge: CNF-Anchored, LLM-Assisted Verilog Generation
Prithwish BASU ROY (New York University), Akashdeep SAHA (New York University Abu Dhabi), Manaar ALAM (New York University Abu Dhabi), Johann KNECHTEL (NYUAD), Michail MANIATAKOS (NYU-AD), Ozgur SINANOGLU (New York University Abu Dhabi), Ramesh KARRI (NYU)

11:30 AM – 12:30 PM Special Session 2: “Security in the Era of Quantum Computing”

Room 2 (Cabernet)

Organizer: Samah Mohamed Saeed
Chair: TBD

Learning Quantum Algorithm Footprints to Evaluate Circuit Obfuscation
Samah Mohamed Saeed (City College of New York)

Hardware Acceleration of PQC Standards
Ramesh Karri (New York University)

Security Issues in multi-tenant quantum computers
Kanad Basu (Rensselaer Polytechnic Institute)

Timing-Based Forensics for Quantum Hardware
Swaroop Ghosh (Penn State University)

11:30 AM – 12:30 PM IP Session 2: “Applying Analog Scan to Industrial Circuits”

Room 3 (Zinfandel)

Organizer: Steve Sunter
Chair: TBD

Diverse needs and challenges in achieving practical and effective analog scan
Degang Chen (Iowa State University)

Steps to 95% defect coverage for analog scan
Ashok Mathur (AMD)

Comparing analog scan and digital scan
Steve Sunter (Siemens Inc)

12:30 PM – 2:00 PM Lunch, Ph.D. McCluskey Competition Poster Session, and PhD Forum Poster Session

Pool Patio

PhD Competition Posters:
Jayeeta CHAUDHURI — From Threats to Trust: Security Strategies for FPGAs and Analog/Mixed-Signal Circuit Design
Michael SEKYERE — Design and test techniques to enhance analog and mixed-signal (AMS) circuits performance and reliability
Sudipta PARIA — Automating SoC Security: An End-to-End AI-Assisted Verification and Protection Framework
Mohamadreza ROSTAMI — Next Generation Hardware Security Testing
Hanzhi XUN — Advanced Testing and Reliability Enhancements for RRAMs
Gabriele FILIPPONI — Manufacturing and In-Field Testing Techniques
Michael ROGENMOSER — From Components to Architecture: An End-to-End Approach to Soft-Error Tolerance
Sanjay DAS — Functional safety of Mission-critical Hardware
Salvatore PAPPALARDO — Investigating Hardware for Resilient Artificial Intelligence

Student Forum Posters:
Davide BAROFFIO — Compiler Technologies for Fault Tolerant Systems
Dipal HALDER — Reconfigurable Topology Obfuscation for NoC-Based SoCs: Protecting Designs Against Reverse Engineering

2:00 PM – 3:00 PM Regular Session 3: “Hardware Security and Trust in Heterogeneous Integration”

Room 1 (Merlot & Syrah)

LEAD: Link Exploitability Analysis for Die-to-Die Interconnects in Heterogeneous Integration
Arjun HATI (Arizona State University), Ortega EDUARDO (ASU), Jonti TALUKDAR (NVIDIA), James PLUSQUELLIC (Univ. of New Mexico), Krishnendu CHAKRABARTY (Arizona State University)

ROCKET: Runtime Operating-Condition Aware KEy Refreshing Technique for Resisting Side-Channel Analysis Attacks
Hasin Ishraq REEFAT, Hossein POURMEHRANI (University of Maryland Baltimore County), Jean-Luc DANGER (Télécom Paris, Institut Polytechnique de Paris), Sylvain GUILLEY (Secure-IC / LTCI, CNRS, Télécom ParisTech / Département d’informatique de l’ENS, CNRS), Naghmeh KARIMI (University of Maryland Baltimore County)

Structural Reconstruction of Analog Circuits Using Graph Neural Networks and Transformers
Dipali JAIN (University of Texas at Dallas), Guangwei ZHAO (The University of Texas at Dallas), Kaveh SHAMSI (University of Texas at Dallas)

2:00 PM – 3:00 PM Special Session 3: “Trustworthy LLMs for Hardware Formal Verification and Reliable Systems”

Room 2 (Cabernet)

Organizer: Hadi Kamali
Chair: TBD

Automation of Polynomial Formal Verification using Large Language Models
Luca Muller (University of Bremen/DFKI)

LoRA-ABFT: Learnable Algorithmic Fault-Tolerance via Low-Rank Adaptation for Reliable VLLM
Farshad Firouzi (Arizona State University)

From Language to Logic: Bridging LLMs and Formal Representations for RTL Assertion Generation
Hadi Kamali (University of Central Florida)

2:00 PM – 3:00 PM McCluskey PhD Competition semi-finals 1

Room 3 (Zinfandel)

TBD

3:00 PM – 4:00 PM Regular Session 4: “Built-In Self-Test: Digital, Analog and Low-Power”

Room 1 (Merlot & Syrah)

Accelerating Analog Test through Firmware-Hardware Driven Parallelism
Krishna Pramod MADABHUSHI, Ayush JAIN, Logan PUCKETT, William JAHNER, Eslam HAG (Medtronic)

Coverage-Aware Scan Chain Reordering under Iso-Power Constraints for Programmable Low-Power LBIST
Yumei HU, Hairui CAI, Xiangheng XIE (Huazhong University of Science and Technology), Yaning WANG (Huawei Technologies Co., Ltd.), Yu HUANG (HiSilicon Technologies Co., Ltd.), Zhipeng LV, Zhouxing SU (Huazhong University of Science and Technology)

High-Purity, Low-Cost DAC-Based Multitone Waveform Generation for Built-In-Self-Test Applications
Emmanuel NTI DARKO, Saeid KARIMPOUR, Degang CHEN (Iowa State University)

3:00 PM – 4:00 PM Special Session 4: “Securing Edge AI Hardware: Emerging Attacks and Multi-Layer Defenses with LLM-Assisted Design”

Room 2 (Cabernet)

Organizer: Farshad Firouzi
Chair: TBD

Can Language Models Secure Hardware? Evaluating Retrieval-Augmented Generation for IP Protection
Soheil Salehi (University of Arizona)

MoD-CiM: A Mixture-of-Defenses Framework Against Power-Hammering Attacks in Multi-Tenant Compute-in-Memory
Farshad Firouzi (Arizona State University)

Large Language Model Agents for Hardware Design and Security Verification: A Survey and AI Accelerator Case Study
Farimah Farahmandi (University of Florida)

Architectural Countermeasures for Memory Access Leakage in Edge LLM Inference on eFPGAs
Hadi Kamali (University of Central Florida)

3:00 PM – 4:00 PM McCluskey PhD Competition semi-finals 2

Room 3 (Zinfandel)

TBD

4:00 PM – 4:30 PM Break

4:30 PM – 5:30 PM Embedded Tutorial: “Practical AI – Embedded Tutorial”

Room 1 (Merlot & Syrah)

Organizer: Li-C Wang
Chair: Jennifer Dworak

Practical AI – Embedded Tutorial
Li-C Wang (UC Santa Barbara)

4:30 PM – 5:30 PM Special Session 5: “Assessment of Security Risks and Defenses in Chiplet”

Room 2 (Cabernet)

Organizer: Naghmeh Karimi
Chair: TBD

CHIPLET FROM CONCEPT TO SILICON
Junie Um (Cadence Design Systems)

360° OVERVIEW OF RISKS WHEN SYSTEM IN PACKAGE WITH INCLUSION OF THIRD-PARTY CHIPLETS
Sylvain Guilley (Secure IC, LTCI, Telecom Paris, Institut Polytechnique de Paris)

FEASIBILITY ASSESSMENT OF CHIPLET-TO-CHIPLET SIDE CHANNEL ATTACKS
Naghmeh Karimi (University of Maryland Baltimore County)

4:30 PM – 5:30 PM Regular Session 5: “Memory Test and Repair”

Room 3 (Zinfandel)

An Effective Built-In Self-Test Scheme for Digital Computing-In Memories with MAC Function
JIN-FU LI, Wen-Ching LIAO, Kai-Hsiang CHANG (National Central University)

Defect-based Testing for SRAM Address Decoders
Ho-Jie HSU, Hsien-Chen LEE, Chun-Yu SHEN, Po-Tsang HUANG (National Yang Ming Chiao Tung University), Shih-Chieh LIN, Yung-Jheng WANG (Realtek Semiconductor Corporation), Ying-Yen CHEN (Realtek Semiconductor Corp.), Chien-Yuan PAO, Hung-Yu LEE (Realtek Semiconductor Corporation), Mango CHAO (National Yang Ming Chiao Tung University)

Efficient Trimming Test Approach for STT-MRAMs with Merged Reference Scheme
JIN-FU LI, Pei-Yun LIN (National Central University)

5:30 PM – 5:45 PM Short Break

5:45 PM – 6:45 PM Panel 1: Predictive Maintenance: Myth or Reality

TBD

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Tuesday, April 28, 2026

7:30 AM – 8:30 AM Registration

Grand Foyer

8:30 AM – 9:30 AM Keynote 2

TBD

9:30 AM – 10:00 AM Break

10:00 AM – 11:00 AM Regular Session 6: “Fault Modeling, Simulation and Defect Analysis”

Room 1 (Merlot & Syrah)

Algorithm-Technology Co-Optimization for Reliable NVM-CAM Systems
Ali NEZHADI, Sina BAKHTAVARI MAMAGHANI, Mehdi TAHOORI (Karlsruhe Institute of Technology)

Pre-processing Functional And Physical Defect Equivalences To Accelerate Cell-Aware Model Generation
Reza KHOSHZABAN (Politecnico di Torino), Gianmarco MONGELLI, Dorian RONGA (LIRMM), Iacopo GUGLIELMINETTI (Guglielminetti), Michelangelo GROSSO (STMicroelectronics s.r.l.), Eric FAEHN (STM), Patrick GIRARD, Arnaud VIRAZEL (LIRMM), Riccardo CANTORO (Politecnico di Torino)

10:00 AM – 11:00 AM Special Session 6: “Reliability Analysis and Hardening of Neural Network for Radiation-Critical Systems”

Room 2 (Cabernet)

Organizer: Luigi DILILLO
Chair: TBD

Reliability Evaluation of Vector-Accelerated Neural Network Inference on a Fault-Tolerant RISC-V SoC under Proton Irradiation
Luigi DILILLO (IES, University of Montpellier, CNRS, Montpellier, France)

Single Event Transient Reliability Analysis & Hardening of NVDLA MAC Unit
Nikolaos Chatzivangelis (University of Thessaly, Greece)

Reliability Analysis Framework on NVDLA mapped Dynamic Neural Networks
Nikolaos Zazatis (University of Thessaly, Greece / University of Manchester, UK / IHP Microelectronics, Germany)

10:00 AM – 11:00 AM IP Session 3: “Silent data corruption”

Room 3 (Zinfandel)

Organizer: Harish Dattaraya Dixit
Chair: Arani Sinha

Resilience approaches in Meta’s MTIA Silicon
J. Nithya (Meta)

Deep Functional Test for Reduction of Silent Data Errors in Data Center Processors
David Lerner (Intel)

11:00 AM – 12:00 PM Regular Session 7: “Reliability and Fault Tolerance in AI Accelerators”

Room 1 (Merlot & Syrah)

ENFOR-SA: End-to-end Cross-layer Transient Fault Injector for Efficient and Accurate DNN Reliability Assessment on Systolic Arrays
Rafael TONNETO (INRIA), Marcello TRAIOLA (Inria), Fernando DOS SANTOS (INRIA), Angeliki KRITIKAKOU (Univ Rennes, INRIA, Irisa)

FT-Sparse: Algorithm-Based Fault Tolerance for Sparse CNNs Using Structured Sparsity in GPUs
Josie RODRIGUEZ CONDIA (Politecnico di Torino), Mohammad Hasan AHMADILIVANI, Maksim JENIHHIN, Jaan RAIK (Tallinn University of Technology), Matteo SONZA REORDA (Politecnico di Torino)

A Flexible Framework for Vector Accelerators In-field Testing
Gustavo VILAR DE FARIAS, Josie RODRIGUEZ CONDIA, Matteo SONZA REORDA, Gustavo VILAR DE FARIAS (Politecnico di Torino)

11:00 AM – 12:00 PM Special Session 7: “Error Correction Techniques For Communication Systems”

Room 2 (Cabernet)

Organizer: Arindam Sanyal
Chair: TBD

Digital calibration/correction on phase-locked loop
Qiaochu Zhang (University of Virginia)

Machine learning calibration for radios
Arindam Sanyal (Arizona State University)

A gm-C Oscillator-Based On-Chip Offset Test and Calibration Technique for Analog Amplifiers
Tejasvi Das (Rochester Institute of Technology)

11:00 AM – 12:00 PM IP Session 4: “Hardware Security & Test”

Room 3 (Zinfandel)

Organizer: Jonti Talukder & Shorab Aftabjahani
Chair: TBD

Addressing security for in-system test and SLM to enable in-field silicon monitoring
Lee Harrison (Siemens)

Scaling Hardware Security Assurance: AI-Driven Solutions Beyond Traditional Testing
Priyam Biswas (Intel)

Pre-Silicon Security Validation of Peripheral Roots of Trust using FPGA Emulation and Fuzzing
Sandhya Koteshwara (IBM Research)

12:00 PM – 1:30 PM Lunch and Late Breaking Results (LBR) Poster Session

Pool Patio

LBR 1: A Systematic Vulnerability Analysis of MRAM-Based Compute-in-Memory against Side-Channel Attacks

Hossein POURMEHRANI (University of Maryland Baltimore County), Yashas KRISHNAMOHAN, Sumukh BHANUSHALI, Saurabh DHIMAN (Arizona State University), Rajendra BISHNOI (Delft University of Technology), Arindam SANYAL, Farshad FIROUZI (Arizona State University), Naghmeh KARIMI (University of Maryland Baltimore County)

LBR 2: Close-to-Functional Tests for Two-Cycle Interconnect Faults

Irith POMERANZ (Purdue University)

LBR 3: Compressed Bit-Level Timing-Error Predictors via Binary Neural Networks

Georgios CHATZITSOMPANIS, Nikolaos KOSTAKIS, Georgios KARAKONSTANTIS (University of Thessaly)

LBR 4: Confidence-Gap-Driven Functional Test Pattern Generation for Enhancing Functional Safety of CNN Accelerators

Tong-Yu HSIEH, Ching-Hsin HSU, Wei-Ji CHAO (National Sun Yat-sen University)

LBR 5: Diagnostic Test Templates for Two-Cycle Gate-Exhaustive Faults

Irith POMERANZ (Purdue University)

LBR 6: Feature-Aware Trojan Alteration to Evade ML-Based Detection

Lizi ZHANG (The University of Wisconsin – Madison), Navid NADER TEHRANI, Azadeh DAVOODI (University of Wisconsin), Rasit TOPALOGLU (Adeia)

LBR 7: High-Throughput Metastability Characterization of Arbiters using HDC-based BIST

Abdullah SAHRURI, Martin MARGALA (University of Louisiana at Lafayette)

LBR 8: New Techniques for Self-Test Library Compaction

Nikolaos DELIGIANNIS, Michelangelo BARTOLOMUCCI, Mansour SOHRABIAN, Riccardo CANTORO, Matteo SONZA REORDA (Politecnico di Torino)

LBR 9: Proton Beam Experiments of Compiler-based Hardware Fault Tolerance

Emilio CORIGLIANO, Davide BAROFFIO, Federico REGHENZANI, Tomas Antonio LOPEZ, William FORNACIARI (Politecnico di Milano)

LBR 10: Test Selection for In-Field Testing Using a Two-Dimensional Aging Space

Irith POMERANZ (Purdue University), Subashini GOPALSAMY (Qualcomm Technologies Inc.), ARANI SINHA (INTEL CORPORATION), Yonsang CHO (Intel Corporation)

1:30 PM – 2:30 PM Regular Session 8: “Emerging Memory Test, Calibration and Reliability”

Room 1 (Merlot & Syrah)

Temporal Reference Scouting Logic for PVT Reliable Logic Computation-in-Memory
shanmukha MANGADAHALLI SIDDARAMU (Karlsruher Institut für Technologie), Ali NEZHADI (Karlsruhe Institute of Technology), Mahta MAYAHINIA (KIT university), Sule OZEV (Arizona State University), Mehdi TAHOORI (Karlsruhe Institute of Technology)

Variation-Aware Post-Manufacturing Calibration for ReRAM-based Content-Addressable Memory
Haneen G. HEZAYYIN (Karlsruhe Institute of Technology), Mahta MAYAHINIA (KIT university), Mehdi TAHOORI (Karlsruhe Institute of Technology)

Experimental Validation of Spatial Autocorrelation Framework for RowHammer Test Optimization
Mohammad FARMANI, Vineet SURESH KUMAR (Florida Polytechnic University)

1:30 PM – 2:30 PM Special Session 8: “Reliability Assessment of DNN Models and Inference on Systolic Arrays”

Room 2 (Cabernet)

Organizer: Maksim Jenihhin
Chair: TBD

SAFPA: Fast analytical reliability assessment for DNN Inference on Systolic Arrays
Maksim Jenihhin (TalTech – Tallinn University of Technology)

Iterative and Conservative Statistical Fault Injections for DNN reliability assessments
Matteo Sonza Reorda (Politecnico di Torino)

FLAUERS: a novel fault injection technique for Systolic Array Accelerated DNNs
Alberto Bosio (Ecole Centrale de Lyon)

1:30 PM – 2:30 PM Panel 2

Room 3 (Zinfandel)

TBD

2:30 PM – 3:30 PM Regular Session 9: “Post-Silicon Validation and Silicon Lifecycle Analytics”

Room 1 (Merlot & Syrah)

Accelerating Recurring Failure Search With AI-Based Scandump Anomaly Pattern Detection
Lay Wai KONG (AMD)

TRACK: Telemetry-based Representation Analysis via Centered Kernel Alignment for Silicon Lifecycle Management
Ortega EDUARDO (ASU), Jonti TALUKDAR (NVIDIA), Hsiao-Ping NI, Krishnendu CHAKRABARTY (Arizona State University)

Next-Gen Scalable In-System-Test Architecture for Nvidia Automotive Platform
Sailendra CHADALAVADA (Nvidia), Milind SONAWANE, Saranyan SARANGAN, Alex HSU, Pavan JAVVAJI (NVIDIA), Shantanu SARANGI (Nvidia)

2:30 PM – 3:30 PM Special Session 9: “2.5D/3D Chiplet-based Integration: New Dimensions in Design and Testing”

Room 2 (Cabernet)

Organizer: Jeff Zhang and Kevin Cao
Chair: TBD

Chiplet System Architecture
David Wentzlaff (Princeton University)

Design Automation of 2.5D/3D Chiplet-based Systems
Yu (Kevin) Cao (University of Minnesota)

Design-for-testability of 3D Integrated Circuits
Krishnendu Chakrabarty (Arizona State University)

2:30 PM – 3:30 PM IP Session 5: “Generative AI Applications to Test and Quality”

Room 3 (Zinfandel)

Organizer: Chen He
Chair: TBD

GenAI Usage for Data Center Quality
Amr Haggag (Arm, Head of Quality)

AI based Automation for NXP DFT Flows
Saidapet Ramesh (NXP Semiconductors, Director of DFT)

GenAI Application to Silicon Lifecycle Management
Fei Su (Tsinghua University, Professor)

3:30 PM – 11:00 PM Social Event

TBD

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Wednesday, April 29, 2026

7:30 AM – 8:30 AM Registration

Grand Foyer

8:30 AM – 9:30 AM Keynote 3

TBD

9:30 AM – 10:00 AM Break

10:00 AM – 11:00 AM Regular Session 10: “ATPG, Scan and Test Compression”

Room 1 (Merlot & Syrah)

C2C: Cell-to-Cell Controllability Evaluation for Partial Scan Selection
Hairui CAI, Zihao WANG (Huazhong University of Science and Technology), Liuzheng WANG, Fei YANG, Mingqi LI (HiSilicon Technologies Co., Ltd.), Lingxiang LIAO (Huazhong University of Science and Technology), Yu HUANG (HiSilicon Co.), Zhouxing SU, Zhipeng LV (Huazhong University of Science and Technology)

Scan Chain Reordering for Improving Test Coverage with Compression
Hairui CAI (Huazhong University of Science and Technology), Zezhong WANG (HiSilicon Technologies Co., Ltd), Yu HUANG (HiSilicon Co.), Naixing WANG (HiSilicon Technologies Co., Ltd.), Zhouxing SU, Zhipeng LV (Huazhong University of Science and Technology)

Compact Functional Test Pattern Generation for DNNs Using Evolution Strategies
Tara GHESHLAGHI (Karlsruhe Institute of Technology, Germany), Dina MOUSSA (Karlsruhe Institute of Technology), Michael HEFENBROCK (Perspix.ai), Mehdi TAHOORI (Karlsruhe Institute of Technology)

10:00 AM – 11:00 AM Special Session 10: “Reliable Emerging Electronics in Wearable and Implantable Healthcare Applications”

Room 2 (Cabernet)

Organizer: Sule Ozev
Chair: Mehdi Tahoori

In-situ monitoring of implantable valves through embedded RF biomechanical signal generator
Jennifer Blain (Arizona State University)

Design of Reliable ADCs for Flexible electronics
Paula Carolina LOZANO DUARTE (Karlsruhe Institute of Technology)

Excitation and Monitoring Circuit Design for Delay-based BIST of LDOs in Flexible Electronics
Sule Ozev (Arizona State University)

10:00 AM – 11:00 AM IP Session 6: “Latest IEEE Test Technology Standards”

Room 3 (Zinfandel)

Organizer: Martin Keim
Chair: TBD

Developments on IEEE standards 1838(a) & 1687
Adam Cron (Synopsys)

Developments on IEEE standard 1687.2
Steve Sunter (Siemens Inc)

Developments on IEEE standard P2929
Shankaran Mennon (Ericsson)

11:00 AM – 12:00 PM Regular Session 11: “Test for 3D Integration, Interconnects and Packaging”

Room 1 (Merlot & Syrah)

NERT: Network- and Routing-aware Testing of Interconnects in Fanout Wafer-Level Packaging
Dhruv THAPAR, Partho BHOUMIK (Arizona State University), Arjun CHAUDHURI (ASU), Krishnendu CHAKRABARTY (Arizona State University)

DART: Dynamic Repair for Interconnect Fault Tolerance in Hybrid Bonding
Partho BHOUMIK (Arizona State University), Zhichao CHEN, Puneet GUPTA (University of California, Los Angeles), Krishnendu CHAKRABARTY (Arizona State University)

WARP-TPG: Warpage-Aware Test Pattern Generation for Small-Delay Defects
Dhruv THAPAR (Arizona State University), Arjun CHAUDHURI (ASU), Krishnendu CHAKRABARTY (Arizona State University)

11:00 AM – 12:00 PM Special Session 11: “Robustness & testability challenges in emerging in-/near-memory computing architectures”

Room 2 (Cabernet)

Organizer: J.-P. Noel and A. Virazel
Chair: TBD

Analysis and Mitigation of PCM Cells Programming Misalignments in Analog In-Memory Computing Cores
A. Antolini (University of Bologna)

Enhancing Testability & Reliability of Near-Memory Computing Architectures through Native Computational Resource Optimization
M. Kooli (CEA/LETI)

Enhancing Robustness of Content-Addressable Memories for In-Memory Search
X. Hu (University of Notre Dame)

11:00 AM – 12:00 PM IP Session 7: “AI Application on VLSI design & test.”

Room 3 (Zinfandel)

Organizer: Arjun Chaudhuri
Chair: TBD

12:00 PM – 1:30 PM Lunch

Pool Patio

1:30 PM – 2:30 PM Regular Session 12: “SoC Test, SEU Resilience and Silent Data Corruption”

Room 1 (Merlot & Syrah)

IABIST: An IJTAG-Compliant Machine Learning-Based Analog BIST Framework for SoC Verification
JULES KOUAMO, Emmanuel SIMEU (TIMA Laboratory), Michele PORTOLAN (Siemens)

Who Checks the Checker Enhancing Component-level Architectural SeU Fault Tolerance for End-to-End SoC Protection
Michael ROGENMOSER (ETHZ), Philippe SAUTER, Chen WU, Angelo GAROFALO, Luca BENINI (ETH Zurich)

SHOUT – Silent Data Corruption Hunting and Observation Using Transformers
Seyedehmaryam GHASEMI (Karlsruher Institute of Technology), shanmukha MANGADAHALLI SIDDARAMU (Karlsruher Institut für Technologie), Tara GHESHLAGHI (Karlsruhe Institute of Technology, Germany), Sani NASSIF (Radyalis LLC), Mehdi TAHOORI (Karlsruhe Institute of Technology)

1:30 PM – 2:30 PM Special Session 12: “Verification, Reliability, and Security Challenges in LLM-Enabled VLSI Design and AI Hardware”

Room 2 (Cabernet)

Organizer: Shaahin Angizi
Chair: TBD

Mitigating ReRAM Non-Idealities in In-Memory Computing Using Noise-Aware Training and Adaptive Experts for Large Language Models
Farshad Firouzi (Arizona State University)

Closing the Loop in LLM-Based Hardware Generation: An Autonomous Agentic Workflow for Robust TPU Design
Shaahin Angizi (New Jersey Institute of Technology)

Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation
Hadi Kamali (University of Central Florida)

Towards LLM-Based Reasoning for Gate-Level Netlist Completion
Lilas Alrahis (Khalifa University)

1:30 PM – 2:30 PM IP Session 8: “TBD”

Room 3 (Zinfandel)

TBD

2:30 PM – 3:30 PM Special Session 13: “Calibration techniques for Radio-Frequency systems”

Room 1 (Merlot & Syrah)

Organizer: Arindam Sanyal
Chair: TBD

Non-Intrusive THz Chiplet Calibration Using Physics-Informed Neural Networks
Morteza Fayazi (University of Utah)

Trust Calibration for RF and Mixed-Signal Systems: A Survey of Lightweight Hardware Security
Ankit Mittal (University of Connecticut)

Analog correlators with applications to low-power radar and spectrum sensing
Aravind Nagulu (Northeastern University)

2:30 PM – 3:30 PM Special Session 14: “Security Vulnerabilities of Semiconductor Memories”

Room 2 (Cabernet)

Organizer: Biswajit Ray
Chair: TBD

Security Vulnerabilities in 3D NAND Flash Memory
Biswajit Ray (Colorado State University)

Are Emerging Memories Secure A Case Study on ReRAM
Biresh Kumar Joardar (University of Houston)

Tracing the Invisible: Unlocking Data from SRAM Aging Imprints
Ujjwal Guin (Auburn University)

2:30 PM – 3:30 PM Panel 3

Room 3 (Zinfandel)

TBD

3:30 PM – 3:45 PM Closing Session