The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems.
The symposium will take place on April 22-24 2024, in Tempe, AZ, USA.
The program includes keynotes, scientific paper presentations, short industrial application paper presentations, special sessions, and Innovative Practices sessions.
You are invited to participate and submit your contributions to VTS’24. The areas of interest include (but are not limited to) the following topics:
VTS Topics
- Analog – Mixed-Signal – RF Test
- ATPG & Compression
- Silicon Debug
- Automotive Test & Safety
- Built-In Self-Test (BIST)
- Defect & Current Based Test
- Defect & Fault Tolerance
- Delay & Performance Test
- Design for Testability – Yield or Reliability
- Pre-silicon Design Verification & Validation
- Post-silicon Validation
- Hardware Security
- Embedded System & Board Test
- Embedded Test Methods
- Emerging Technologies Test and Reliability
- Fault Modeling and Simulation
- Low-Power IC Test
- Functional safety and test methods to ensure functional safety
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- Machine Learning in Test – Yield and Reliability
- Microsystems/MEMS/Sensors Test
- Memory Test and Repair
- 2.5D – 3D & SiP Test
- Yield Optimization
- On-Line Test & Error Correction
- Power & Thermal Issues in Test
- System-on-Chip (SOC) Test
- Test & Reliability of Biomedical Devices
- Test & Reliability of High-Speed I/O
- Test & Reliability of Machine Learning Systems
- Test Quality & Reliability
- Test Standards & Economics
- Test Resource Partitioning
- Transient & Soft Errors
- FPGA Test
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New Hot Topics
This year, VTS puts particular emphasis on enlarging its scope soliciting submissions on aspects on silent data corruption test, reliability and security of AI, fault models and reliability of in-memory computing hardware, and quantum computing, and functional safety.
