Algorithm to Architecture to RTL to GDSII: Incorporating Security into All Phases of SoC Design and Implementation Flow

Speaker: Mr. Serge Leef, DARPA MTO PM

April 26, 7:15 am PDT

Abstract: In approaching hardware security, we need consider each of the major stages of the IC design and implementation process.
This talk will examine the vulnerabilities and defense strategies for the three stages of design: algorithm to architecture, architecture to RTL, and RTL to GDSII against supply chain, side-channel, reverse engineering and malicious implant attack surfaces.

Speaker bio: Mr. Serge Leef joined DARPA in August 2018 as a program manager in the Microsystems Technology Office (MTO). His research interests include computer architecture, chip design tools, simulation, synthesis, semiconductor intellectual property (IP), cyber-physical modeling, distributed systems, secure design flows, and supply chain management. He is also interested in the facilitation of startup ecosystems and business aspects of technology.

Leef came to DARPA from Mentor, now Siemens EDA, where from 2010 until 2018 he was a Vice President of New Ventures, responsible for identifying and developing technology and business opportunities in systems-oriented markets. Additionally, from 1999 to 2018, he served as a division General Manager, responsible for defining strategies and building successful businesses around design automation products in the areas of hardware/software co-design, multi-physics simulation, IP integration, SoC optimization, design data management, automotive/aerospace networking, cloud-based electronic design, Internet of Things (IoT) infrastructure, and hardware cybersecurity.

Prior to joining Mentor, he was responsible for design automation at Silicon Graphics, where he and his team created revolutionary, high-speed simulation tools to enable the design of high-speed 3D graphics chips, which defined the state-of-the-art in visualization, imaging, gaming, and special effects for a decade. Prior to that, he managed a CAE/CAD organization at Microchip and developed functional and physical design and verification tools for major 8- and 16-bit microcontroller and microprocessor programs at Intel.

Leef received his Bachelor of Science degree in electrical engineering and Master of Science degree in computer science from Arizona State University. He has served on corporate, state, and academic advisory boards, delivered numerous public speeches, and holds patents in hardware Trojan detection and Internet of Things (loT) infrastructure.

Edge Computing Trends, Design and Test Challenges

Speaker: Dr. Karim Arabi, Atlazo Inc.

April 27, 7:00 am PDT

Abstract: As a natural evolution of Cloud Computing, we are starting to move more computing tasks to the edge. This enables better response time and reduces data overload while offering enhanced privacy and lower power consumption. Edge Computing is addressing applications where real-time processing of data is required or volume of generated data cannot be transferred to the Cloud. This talk presents major Edge Computing trends and covers challenges related to design, test and reliability of Edge Computing systems.

Speaker bio: Dr. Karim Arabiis co-founder and CEO of Atlazo, Inc. developing ultra-low power AI semiconductor and software for edge computing applications targeting earbuds, wearable and health monitoring markets. Previously, VP of R&D and Engineering at Qualcomm, he led advanced wireless and computing technologies and mobile SoC design. He was VP, Engineering at Dialog Semiconductor working on semiconductor products for mobile devices. As an entrepreneur, Dr. Arabi has had several successful startup exits in the semiconductor sector. Karim obtained his Ph.D. and M.Sc. in Electrical Engineering from Polytechnique Montréal, Canada and his B.Sc. in Electrical Engineering from Tehran Polytechnic.