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GENERAL INFO
PRACTICAL INFO
PROGRAM
SUBMISSIONS
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Tutorials |
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VLSI Test Symposium 2012 includes an excellent TTEP 2012 tutorial on high interesting
and interdisciplinary technology topic. This tutorial qualifies for IEEE TTTC certification and will be presented on Thursday,
April 26th (8:30am-4:40pm). The tutorial requires a separate fee and registration.
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Tutorial 1: Thursday, April 26th |
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8:30 am - 4:40 pm VLSI Test and Security
PRESENTERS: Ramesh Karri (NYU-Poly), Peilin Song (IBM T.J. Watson), Ozgur Sinanoglu (NYU Abu Dhabi)
AUDIENCE:
This tutorial is most suitable for DFT and Test Engineers, Validation and Verification engineers, Researchers and
students in DFT, testing and validation, hardware security.
DESCRIPTION:
Hardware security and trust is an important design objective similar to power, performance, reliability and testability. We will highlight why hardware security and trust are important objectives from the economics, security, and safety perspectives. Important learning outcomes of this tutorial include (i) understanding simple gotchas when traditional DFT, test, and validation techniques are used (scan chains, JTAG, SoC test, assertion based validation), (ii) understand how traditional DFT, test and validation techniques can be used to improve hardware security and trust and finally (iii) understand "Design for Trust" approaches that can provide testability without compromising security and trust.
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DEADLINES
Registr. cutoff: Apr. 12th
Hotel cutoff: Apr. 1st
Abstract: Oct. 8th '11
PDF: Oct. 21st - extended
Special Sess.: Nov. 15th '11
IP Sess.: Nov. 15th '11
Notification: Jan. 7th '12
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