Monday, April 23rd

7:30AM - 8:30AM Registration and Breakfast

8:30am-10:45am   Plenary Session (Regency A&B)

10:45AM - 11:15AM Break

11:15AM - 12:15PM Sessions 1

• Test Generator with Preselected Toggling for Low Power Built-In Self-Test
  J. TYSZER - Poznan U. of Technology, J. RAJSKI, G. MRUGALSKI, B. NADEAU-DOSTIE - Mentor Graphics
• A Built-In Self-Test Scheme for DDR Memory Output Timing Test and Measurement
  H. KIM, J. ABRAHAM - U. of Texas
• HBIST: An Approach towards Zero External Test Cost
  M. BUBNA, A. GOEL K. ROY - Purdue U.

• Smart selection of indirect parameters for DC-based alternate RF IC testing
  F. AZAIS, H. AYARI, S. BERNARD, M. COMTE, M. RENOVELL, V. KERZERHO - LIRMM, C. KELMA - NXP, O. POTIN - LIRMM
• Analog/RF test ordering in the early stages of production testing
  N. AKKOUCHE, S. MIR, E. SIMEU - TIMA, M. SLAMANI - IBM
• A SAR ADC Missing-Decision Level Detection and Removal Technique
  X.L. HUANG, J. L. HUANG - National Taiwan U., Y.F. CHOU, D.M. KWAI - ITRI

Abstract: Failures in chips seen during manufacturing tests, application board bring-up or in the field at customer site are major sources of concerns to both semiconductor manufacturers and customers. Various chip design trends, primary of them being short customer lead times, have placed a premium on chips and the systems using them to be working as intended in the shortest time possible! Robust post-silicon debug and failure analysis practices are needed to meet these expectations. This IP session will expose the VTS audience to unique and recent post-silicon debug experiences/practices of leading chip vendors, along with latest and greatest in failure analysis technologies.

• Case studies of root-causing critical failures and test escapes on TI's Platform SoCs
  B. Duggal (speaker), A. Bhat, P. Pradeep, H. Mistry, A. Jain - Texas Instruments
• Fault isolation through optical diagnostics and nano-probing: A critical bridge between scan-based diagnosis and failure analysis.
  T. Eiles - Intel
• A fault diagnosis system having interfaces to various DFT tools
  K. Shigeta - Renesas Technologies

12:15PM - 1:45PM Lunch

1:45PM - 2:45PM Sessions 2

• Self-Adaptive Power Gating with Test Circuit for On-line Characterization of Energy Inflection Activity
  A. TRIVEDI, S. MUKHOPADHYAY - Georgia Institute of Technology
• Comprehensive Online Defect Diagnosis in On-Chip Networks
  A. GHOFRANI - UC Santa Barbara, R. PARIKH - U. of Michigan at Ann Arbor, S. SHAMSHIRI - UC Santa Barbara, A. DEORIO, V. BERTACCO - U. of Michigan at Ann Arbor, K.T. CHENG - UC Santa Barbara
• A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures
  D. A. TRAN, A. VIRAZEL, A. BOSIO, L. DILILLO, P. GIRARD, A. TODRI - LIRMM, M. IMHOF, H.J. WUNDERLICH - U. Stuttgart

• Built-in-Self Test of Transmitter I/Q Mismatch Using Self-Mixing Envelope Detector
  A. NASSERY, S. BYREGOWDA, S. OZEV - Arizona State U., M. VERHELST - Katholieke U. Leuven , M. SLAMANI - IBM
• Towards a Fully Stand-Alone Analog/RF BIST: A Cost-Effective Implementation of a Neural Classifier
  D. MALIUK, N. KUPP, Y. MAKRIS - Yale U.
• An On-Chip NBTI Monitor for Estimating Analog Circuit Degradation
  S. ASKARI, M. NOURANI, M. RAWAT - U. of Texas at Dallas

Abstract: This session presents advanced approaches for testing of nowadays memories which cover test engine architecture, test optimization and their ease of use.
With aggressive deployment of newer technologies and increasing amount of embedded memories in today's SoCs, it has become very crucial to ensure quick silicon bring-up and fast design ramp-up, enabling extensive silicon data collection for process/design characterization along with effective test mimicking the complete functional use mode. Here, innovative design and test practices are presented that are deployed on multiple sub-45nm industrial designs towards addressing the above goals. Various diverse practices such as tester-aware test optimization, test pattern optimization to enable quick characterization and silicon data collection, physical-aware test planning, techniques for functional-use mode test generation and design and test hooks to enable effective stress test are presented. Also a few case-studies are presented to illustrate the benefits of the proposed schemes.
A new built-in self-test (BIST) architecture is proposed. It provides mechanisms to program not only test algorithms but also test operations and background patterns. This solution allows defining new test mechanisms at any stage of design and finding the best trade-off between BIST complexity and the requirements for testing memories. Also a technique for BIST hardware optimization is suggested. Optimization experiments show that the BIST hardware gain could reach 20-30% with negligible time overhead.

• Novel approaches for effective and optimized memory test flow in nanoscale technologies
  V.R. Devanathan, R. Mehrotra, P.S. V. Kumar, V. Sarkar, I. M. Beg, Sh. Bathla - Texas Instruments
• Advanced architecture for memory BIST
  Y. Zorian - Synopsys
• Memory Test Challenges in Complex SOCs
  Ch. Dixit, S. Chakravarty, LSI

2:45PM - 3:00PM Break

3:00PM - 4:00PM Sessions 3

• An Oscillation-based Test Structure for Post-Silicon Timing Information Extraction
  E. J. JANG - U. of Texas at Austin , A. GATTIKER , S. NASSIF - IBM , J. ABRAHAM - U. of Texas at Austin
• Silicon Evaluation of Faster than at-speed Transition Delay Tests
  S. CHAKRAVARTY, N. DEVTA-PRASANNA, A. GUNDA, F. YANG - LSI, J. MA - U. of Connecticut , H. GUO, R. LAI, D. LI - LSI
• Bayesian-Based Process Parameter Estimation Using IDDQ Current Signature
  M. SHINTANI, T. SATO - Kyoto U.

• Identifying test issues with nano-scale optics: considerations at the quantum level
  C. LANDROCK - iDme Technologies

• Introduction to FPGA-based Test
  J. DWORAK - Southern Methodist U.
• IP for for Protocol-Aware FPGA-based Test
  A. CROUCH - ASSET InterTech
• Accessing Embedded Tester IP
  A. CROUCH - ASSET InterTech

4:00PM - 4:15PM Break

4:15PM - 5:45PM Sessions 4

Tuesday, April 24th

7:30AM - 8:30AM Breakfast

8:30AM - 9:30AM Sessions 5

• Direct Connection and Testing of TSV and Microbump Devices using NanoPierce Contactor
  O. YAGLIOGLU, B. ELDRIDGE - FormFactor
• Test Cost Optimization Technique for Pre-Bond Test of 3D ICs
  J. F. LI, Y.X. CHEN, Y.J. HUANG - National Central U.
• Cost Modeling and Analysis for Interposer-Based Three-Dimensional IC
  Y.W. CHOU, P.Y. CHEN , M. LEE, C.W. WU - National Tsing Hua U.

• Delay Test Resource Allocation and Scheduling for Multiple Frequency Domains
  B. ARSLAN, A. ORAILOGLU - UC San Diego
• Detection of Gate-Oxide Defects with Timing Tests at Reduced Power Supply
  X. QIAN, C. HAN, A. SINGH - Auburn U.
• Small-Delay Defects Detection Under Process Variation Using Inter-Path Correlation
  F. GALARZA-MEDINA, J. GARCIA-GERVACIO, V. H. CHAMPAC - INAOE, A. ORAILOGLU - UC San Diego

• Solving the Soft Error conundrum on SoC with innovative analytic tools
  O. LAUZERAL, D. ALEXANDRESCU - iRoC
• A Predictive Bottom-up Hierarchical Approach to System Reliability
  V. HUARD - STMicroelectronics, L. ANGHEL - TIMA
• DFH(eterogeneity) for tera-scale reliable processors
  X. VERA - Intel

9:30AM - 9:45AM Break

9:45AM - 10:45AM Sessions 6

• Test of Phase Interpolators in High Speed I/Os Using a Sliding Window Search
  J. CHUN, S. M. LIM, S. C. ONG - Intel, J. W. LEE - Computer Engineering Research Center, J. ABRAHAM - U. of Texas at Austin
• Dual-frequency Incoherent Sub-sampling Technique for Signal Reconstruction of Spectrally Sparse Wideband Signals with Enhanced Time/Frequency Resolution
  N. TZOU - Georgia Institute of Technology
• Jitter Characterization of High-Speed Pseudo-Random Bit Sequences Using Nonuniform Periodic Sampling with Low-cost Hardware Architecture
  T. H. MOOG, H. CHOI, A. CHATTERJEE - Georgia Institute of Technology

• Enhancing Testability by Structured Partial Scan
  P WOHL, J. WAICUKAUSKI - Synopsys , J. COLBURN - Nvidia
• Write-through Method for Embedded Memory with Compression Scan-based Testing
  G. SEOK, H. KIM - Qualcomm , B. MOHAMMAD - Khalifa U. of Science
• Ping-pong Test: Compact Test Vector Generation for Reversible Circuits
  M. ZAMANI - Northeastern U. , M. TAHOORI - Karlsruhe Institute of Technology , K. CHAKRABARTY - Duke U.

10:45AM - 11:00AM Break

11:00AM - 12:00PM Sessions 7

• SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms
  A. CZUTRO, M. SAUER, T. SCHUBERT - U. of Freiburg , I. POLIAN - U. of Passau , B. BECKER - U. of Freiburg
• Static Test Compaction for Transition Faults Under the Hazard-Based Detection Conditions
  I. POMERANZ - Purdue U.
• Exploiting X-Correlation in Output Compression via Superset X-Canceling
  J. CHUNG, N. TOUBA - U. of Texas at Austin

• DFT methodology for 3D stacked integrated circuits
  J. NARSINGHANI - CMC Microsystems

• Nand Flash Memory: The Driving Technology in Digital Storage - Technology Overview, Challenges and Future Trends
  M. A. d'Abreu - SanDisk Corp

12:00PM - 1:30PM Lunch

1:30PM - 3:00PM Sessions 8

5:00PM - 10:00PM Social Event

Wednesday, April 25th

7:30AM - 8:30AM Breakfast

8:30AM - 9:30AM Sessions 9

• A Novel Method for Fast Identification of Peak Current during Test
  W. ZHAO, M. TEHRANIPOOR - U. of Connecticut , S. CHAKRAVARTY, N. DEVTA-PRASANNA, J. MA, F. YANG - LSI
• A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits
  K. MIYASE - Kyushu Institute of Technology , M. ASO, R. OOTSUKA - Renesas Micro Systems , X. WEN - Kyushu Institute of Technology , H. FURUKAWA - Renesas Micro Systems , Y. YAMATO - Fukuoka Industry, Science & Technology Foundation , K. ENOKIMOTO, S. KAJIHARA - Kyushu Institute of Technology
• Power Characterization of Embedded SRAMs for Power Binning
  Y. ZHAO, L. GRENIER, A. MAJUMDAR - AMD

• Tester-Based Optical and Electrical Diagnostic System and Techniques
  P. SONG - IBM, F. STELLARI - IBP
• A SMT-Based Diagnostic Test Generation Method for Combinational Circuits
  S. PRABHU, M. HSIAO - Virginia Tech, L. LINGAPPAN, V. GANGARAM - Intel
• Net Diagnosis Using Stuck-at and Transition Fault Models
  L. ZHAO, V. AGRAWAL - Auburn U.

9:30AM - 9:45AM Break

9:45AM - 10:45AM Sessions 10

• Test Algorithms for ECC-based Memory Repair
  P. PAPAVRAMIDOU, M. NICOLAIDIS - TIMA
• A Memory Failure Pattern Analyzer for Memory Diagnosis and Repair
  B.Y. LIN, M. LEE, C.W. WU - National Tsing Hua U.
• Process Variability-Aware Proactive Reconfiguration Technique for Mitigating Aging effects in Nano Scale SRAM lifetime
  A. RUBIO, P. POUYAN, E. AMAT - U. Politecnica de Catalunya

• Are advanced DFT structures sufficient for preventing scan-attacks?
  J. DAROLT, G. DI NATALE, M.L. FLOTTES, B. ROUZEYRE - LIRMM
• Proof Carrying-Based Information Flow Tracking for Data Secrecy Protection and Hardware Trust
  Y. JIN, Y. MAKRIS -Yale U.
• Test Generation for Subtractive Specification Errors
  P. LEE, I. HARRIS - UC Irvine

10:45AM - 11:00AM Break

11:00AM - 12:00PM Sessions 11

• On the Parametric Failures of SRAM in a 3D-die Stack considering Tier-to-Tier Supply Cross-talk
  W. YUEH, S. CHATTERJEE, A. TRIVEDI, S.l. MUKHOPADHYAY - Georgia Institute of Technology
• Transition delay fault testing of 3D-ICs with IR drop study
  S. PANTH, S. K. LIM - Georgia Institute of Technology
• Estimating Power Supply Noise and Analyzing Its Impact on Path Delay
  S. RAO, A. KALLIANPUR, R. ROBUCCI, C. PATEL - UMBC

• Derating Based Hardware Optimisations in Soft Error Tolerant Designs
  V. PRASANTH, R. PAREKHJI -Texas Instruments India, V. SINGH - Indian Institute of Science.
• Towards Spatial and Temporal Fault Resilience in Array Processors
  S. SINDIA, V. AGRAWAL - Auburn U.
• An Aging-Aware Flip-Flop Design Based on Accurate and Robust Failure Prediction
  J. PARK, J. ABRAHAM - U. of Texas at Austin

12:00PM - 1:15PM Lunch

1:15PM - 2:45PM Sessions 12