The aim of the Third TTTC Doctoral Thesis Award is to promote and strengthen the interaction
between doctoral students who are about to graduate and the industrial community. More...
VLSI Test Symposium 2007 includes three excellent TTEP 2007 tutorials on high interest
test technology topics. All three tutorials qualify for IEEE TTTC certification. One tutorial will be presented on Sunday,
May 6th and two on Thursday, May 10th. Each tutorial requires a separate fee and registration.
Tutorial 1: Sunday, May 6th, 8:30-16:30
7:30 - 8:30 am Tutorial Registration, Coffee Service
8:30 am - 4:30 pm Scan Delay Testing of Nanometer SOCs
PRESENTER: Adit Singh (Auburn University)
AUDIENCE: VLSI Design and Test engineers and researchers, engineering managers and also reliability engineers and managers.
DESCRIPTION: Delay defects that degrade performance and cause timing related failures are emerging as a major problem in nanometer
technologies. Structural scan based delay testing is being pursued as a possible cost effective solution for this problem.
However, recent research indicates that several formidable challenges must be overcome before it can become fully effective.
These include poor coverage of launch-on-capture scan test, and also that the observed signal timing may not reflect true
circuit delays in normal functional operation due to false paths, power supply noise, clock stretching etc. This tutorial
aims at a comprehensive discussion of these challenges, along with proposed solutions, mainly aided by data from industrial studies.
Tutorial 2: Thursday, May 10th, 8:30-16:30
7:30 - 8:30 am Tutorial Registration, Coffee Service
8:30 am - 4:30 pm Dealing with Timing Issues for sub-100n Designs - from Modeling to Mass Production
PRESENTERS: Li-C Wang (University of California Santa Barbara), Magdy Abadir (Freescale)
AUDIENCE: Test and debug engineers, researchers, and tool developers who are interested in understanding the impacts of
sub-100 manufacturing processes on timing and in learning how to model them, analyze them, and deal with them at various stages
of design, from library development to silicon test and debug
DESCRIPTION:
This tutorial intends to give attendees an overall picture on timing issues induced by process variations with sub-100n
manufacturing processes. The issues can be divided into three parts: (1) modelling, (2) analysis, and (3) test and debug.
In the modelling part, the tutorial covers the issues of statistical process characterization. It discusses how variation
models are characterized with test structures and how these models can be used to in analyzing timing. Then, timing analysis
and statistical timing analysis is discussed. How timing problems are debugged on silicon and how to devise a reliable speed
binning strategy is then covered. Industrial results are discussed on correlating functional tests to structural tests in speed
binning as well as experiments on correlating delay test results back to timing analysis results. This tutorial emphasizes the
connections between pre-silicon modelling and analysis and post-silicon test and debug methodologies
Tutorial 3: Thursday, May 10th, 8:30-16:30
7:30 - 8:30 am Tutorial Registration, Coffee Service
8:30 am - 4:30 pm DFX: The Convergence of Yield, Manufacturing, and Test
PRESENTERS: Robert Aitken (ARM)
AUDIENCE:
Test practitioners (engineers, students, academics) who are interested in learning more about the interaction between design
and test, as they relate to yield, manufacturability and variability, and how they will affect chips in sub-90nm process technology
DESCRIPTION:
The tutorial goal is to show how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we
conventionally think of as test, and that as process geometries shrink, the line between defects and process variation blurs to
the point where it is essentially non-existent. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less
common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). This tutorial
provides background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate
goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs
LOCATION
VTS will take place from May 6th to May 10th, 2007 in Berkeley, California, USA More...
Moreover, The VTS Organizing Committee is interested in providing a rich
historical view of VTS. Please send information you believe to be relevant
to the historian.
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