Registration desk will be open
- Mon 7:30AM-3PM
- Tues 7:30AM-2PM
- Wednesday 7:30AM-12PM
VTS 2025 Final Program
09:00
Talk Title: Overview of DoD’s Microelectronics
Session Moderator: Krishnendu Chakrabarty (Arizona State U.)
10:30
Regular Session 1: Hardware Security - 1 (MU 230 Pima)
Challenge Selection for Salvaging Faulty APUFs
Speaker: Yeqi Wei (University of Illinois Chicago)
Authors: Yeqi WEI,
Wenjing RAO (University of Illinois Chicago),
Natasha DEVROYE (University of Illinois Chicago)
SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection
Speaker: Tanzim Mahfuz (University of Maine)
Authors: Tanzim MAHFUZ (University of Maine), Pravin GAIKWAD (University of Florida), Tasneem SUHA (University of Maine), Swarup BHUNIA (University of Florida), Prabuddha CHAKRABORTY (University of Maine)
SCAPEgoat: Side Channel Analysis Library
Speaker: Dev Mehta (WPI)
Authors: Dev MEHTA, Trey MARCANTONIO (Worcester Polytechnic Institute), Mohammad HASHEMI, Samuel KARKACHE, Dillibabu SHANMUGAM, Patrick SCHAUMONT (Worcester Polytechnic Institute (WPI)), Fatemeh GANJI (Worcester Polytechnic Institute)
Special Session 1: Advanced Semiconductor Packaging and Test (MU 242 La Paz)
Session Organizer: Leslie Hwang (ASU) & Christopher Bailey (ASU)
From Design to Inspection: Can Inspection-aware Design Enhance Reliability in Advanced Packaging?
Speaker: Navid Asadi (UF)
Test Complexity in the Semiconductor Landscape
Speaker: Suma Ayyagari (Intel)
Reliability Challenges for Advanced Packaging
Speaker: Christopher Bailey (ASU)
IP Session 1: AI for Test (MU 228 Cochise)
Session Organizer: Arjun Chaudhuri, NVIDIA
AI Driven Test Space Optimization
Speaker: Sri Ganta, Synopsys
Towards Test Quality and Productivity Improvement with AI
Speaker: Bonita Bhaskaran, NVIDIA
Emerging Trends in AI for Semiconductor Testing: From Automation to Intelligence
Speaker: Vijayaprabhuvel Rajavel, HCL America Inc.
11:30
Regular Session 2: Yield and Reliability - 1 (MU 230 Pima)
ML-based Adaptive Wafer Sort to Preserve Diagnostic Information
Speaker: Min-Hsin Liu (National Taiwan University)
Authors: Yun-Sheng LIU, Min-Hsin LIU (National Taiwan University), Chien-Mo LI (NTU)
Multi-core Vmin and Worst-core Vmin Prediction using SOMAC
Speaker: Liyang Wang (National Taiwan University)
Authors: Jeng-Yu LIAO, LiYang WANG (National Taiwan University), Chien-Mo LI (NTU), Harry CHEN (MediaTek Inc.)
Reliable Board Level Degradation Prediction with Monotonic Segmented Regression under Noisy Measurement
Speaker: Yuxuan Yin (UC Santa Barbara)
Authors: Yuxuan YIN (University of California, Santa Barbara), Rebecca CHEN, Varun THUKRAL, Chen HE (NXP Semiconductor), Peng LI (University of California, Santa Barbara)
Session Organizer: Wilson PRADEEP (Google)
LLM- Driven Functional Test Generation for Silent Data Corruption (SDC)
Speaker: Farshad FIROUZI (ASU)
Understanding Path Delay Failures from Process Variations for Enhanced Detection and Mitigation
Speaker: Adit SINGH (Auburn)
Understanding the Impact of Transient Hardware Failures in Quntized Neural Networks
Speaker: Yanjing Li
IP Session 2: Hardware Security and Test for AMS Circuits (MU 242 La Paz)
Session Organizer: Arjun Chaudhuri, NVIDIA
A few key aspects of analog defect simulation
Speaker: Mayukh Bhattacharya, Synopsys
Connecting the dots from mathematical to physical security
Speaker: Archisman Ghosh, Ixana
Machine learning assisted testing of AMS circuits
Speaker: Suhasini Komarraju/Suma Ayyagari, Intel
14:00
Talk Title: Towards Zero-ppb Defects in Analog/Mixed-signal ICs
Session Moderator: Naghmeh Karimi (U. Maryland Baltimore County)
15:00
Session Organizer: Farshad Firouzi (ASU)
LLM-Aided Design
Speaker: Farshad Firouzi
LLM for Analog Circuit Design
Speaker: David Z. Pan
Leveraging LLMs for Physical Side-Channel Modeling and Analysis
Speaker: Nader Sehatbakhsh
Electronic-Photonic Heterogeneous Computing Systems for Generative AI Acceleration
Speaker: Jiaqi Gu
Regular Session 3: Aging and Radiation (MU 242 La Paz)
Chip Aging and Double Transition Faults
Speaker: Irith Pomeranz (Purdue University)
Authors: Irith POMERANZ (Purdue University)
Novel Gate Leakage Current Integration-Based Dielectric Breakdown Monitor in a 12nm FinFET Process
Speaker: Mateo Rendon (University of British Columbia)
Authors: Mateo RENDON, Ian HILL, Andre IVANOV (University of British Columbia)
Designing Radiation-Hardened D Flip-Flop with Reduced Latency and Area Using Filtering Buffer
Speaker: Meng-Chen Wu (National Yang Ming Chiao Tung University)
Authors: Nelson M.-C. WU, Lowry P.-T. WANG, Chia-Wei LIANG, Charles H.-P. WEN, Herming CHIUEH (National Yang Ming Chiao Tung University)
Special Session 4: Trustworthy Hardware-AI at the Cloud (MU 228 Cochise)
Session Organizer: Annachiara Ruospo (Politecnico Di Torino) and Arani Sinha (Intel)
SDC/SDE in hardware: Definition and Possible Origins
Speaker: Francesco Angione, Politecnico di Torino
SDC/SDE impact on AI training workload
Speaker: Harish Dattatraya Dixit (Meta)
SDC/SDE impacts on AI inference workload
Speaker: Alberto Bosio, Ecole Centrale De Lyon
16:30
Regular Session 4: Fault Modeling and Analysis (MU 230 Pima)
Fault modeling and Testing of ReRAM-based CAM Array
Speaker: Mehdi Tahoori (Karlsruhe Institute of Technology)
Authors: Haneen G. HEZAYYIN (Karlsruhe Institute of Technology), Mahta MAYAHINIA (KIT university), Mehdi TAHOORI (Karlsruhe Institute of Technology)
Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation
Speaker: Mehmet Onder (Arizona State University)
Authors: Mehmet ONDER (Arizona State University), Lakshmanan BALASUBRAMANIAN (Texas Instruments (India) Pvt.), Rubin PAREKHJI (Texas Instruments (India)), Suriyaprakash NATARAJAN (Siemens EDA), Sule OZEV (Arizona State University)
MicroFI: Tensorflow Lite based Fault Injection Framework for Microcontrollers
Speaker: Leonardo Alexandrino (Nanotechnology Institute of Lyon)
Authors:Leonardo ALEXANDRINO DE MELO, ALBERTO BOSIO (Lyon Institute of Nanotechnology), Rodrigo POSSAMAI BASTOS (TIMA Laboratory (CNRS) / Universit)
Session Organizer: Hadi M Kamali (UCF)
GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness
Speaker: Ozgur Sinanoglu
LLM-Guided Functional Test Generation for COTS Hardware
Speaker: Swarup Bhunia
LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardware
Speaker: Kimia Azar
Fine-Tuning Large Language Models for Hardware Vulnerability Detection in SoC Design
Speaker: Farimah Farahmandi
Regular Session 5: Built In Self Test (MU 242 La Paz)
Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging
Speaker: Partho Bhoumik (Arizona State University)
Authors: Partho BHOUMIK, Chris BAILEY, Krishnendu CHAKRABARTY (Arizona State University)
High Accuracy, Cost-Effective Built-In Self-Test (BIST) Approach for High-Resolution Data Converters
Speaker: Degang Chen (Iowa State University)
Authors: Emmanuel NTI DARKO, Saeid KARIMPOUR, Degang CHEN (Iowa State University)
Periodic Non-Destructive Memory BIST for Automotive Applications
Speaker: Wei Zou (Siemens EDA)
Authors: Wei ZOU, Artur POGIEL, Albert AU, Martin Keim (Siemens EDA)
08:30
Keynote 3: Challenges in Testing and Reliability of BioChips (MU 230 Pima)
Talk Title: Challenges in Testing and Reliability of BioChips
Session Moderator: Sule Ozev (Arizona State U.)
09:30-11:00
-10:00
Regular Session 6: Test Pattern Generation (MU 230 Pima)
Fine-Grained Steepening of the Fault Coverage Curve of a Pool of Functional Test Sequences
Speaker: Irith Pomeranz (Purdue University)
Authors: Irith POMERANZ (Purdue University)
Test Methodology for Detecting Defect-Based Hold-Time Faults
Speaker: Guan-You Chen (National Yang Ming Chiao Tung University)
Authors: Cheng-Hsiang TSAI, Yu-Teng NIEN, Guan-You CHEN, Mango CHAO (National Yang Ming Chiao Tung University)
Timing-Verification Test Generation Targeting Small Delay Defects
Speaker: Jiezhong (Jay) Wu (Purdue University)
Authors: Jiezhong WU (Purdue University), Nilanjan MUKHERJEE (Siemens Digital Industries Software), Irith POMERANZ (Purdue University), Kun-Han TSAI, Janusz RAJSKI (Siemens Digital Industries Software)
Session Organizer: Ken Butler (Advantest)
Heterogeneous Integration Roadmap Test Chapter Overview
Speaker: Jeorge Hurtarte (Teradyne)
Challenges for High Performance Computing Advanced Packaging Products
Speaker: Janusz Rajski
Challenges for devices with Co-Packaged Optics
Speaker: Dave Armstrong
Session Organizer: Arjun Chaudhuri, NVIDIA
Latency Estimation for Large Language Models on Mobile GPUs
Speaker: Chandramouli Amarnath, Google
Can AI transform test
Speaker: Gaurav Veda, Siemens EDA
Al guided Security and Test of Analog Integrated circuits
Speaker: Jonti Talukdar, NVIDIA
11:00
Special Session 7: Using HLS4ML for Testable AI Hardware Designs (MU 228 Cochise)
Session Organizer: Seda Ogrenci (Northwestern U.)
SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated HLS
Speaker: Rui Shi (Northwestern U.)
Gradient Attention Map Based Verification of Deep Convolutional Neural Networks with Application to
Speaker: Enis Cetin (UIC)
From Signals to Features to Insights: Multi-Level Novelty Detection for Fast Scientific Discovery
Speaker: Trivedi, Amit (UIC)
Regular Session 7: Fault Diagnosis and Characterization (MU 230 Pima)
APT: Optimal Tree for Diagnosis Simulation
Speaker: Wu-tung Cheng (Siemens EDA)
Authors: wu-tung CHENG (Siemens)
CHEF: CHaracterizing Elusive Logic Circuit Failures
Speaker: Ruben Purdy (Carnegie Mellon University)
Authors: Ruben PURDY, Chris NIGH, Wei LI (Carnegie Mellon University), Shawn BLANTON (Carnegie Mellon Univ., Pittsburgh, USA)
DC Stimulus Electrical Calibration of MEMS Accelerometers
Speaker: Ishaan Bassi (Arizona State University)
Authors: Ishaan BASSI, Sule OZEV (Arizona State University)
Special Session 8: Test and reliability of THz IC design (MU 242 La Paz)
Session Organizer: Kexin Li (ASU)
Opportunities for Built-in Self-Test Within Emerging mm-Wave Phased Array and MIMO
Speaker: Negar Reiskarimian (MIT)
Modeling of Distortion Behavior of GaN-based HEMTs for High-Frequency IC Design
Speaker: Kexin Li (ASU)
Small-Signal and Large-Signal Measurement Techniques at Sub-THz Frequencies
Speaker:Aritra Banerjee (UIC)
13:15
Ph.D. Competition (MU 230 Pima)
| Student Name | Affiliation | Advisor |
|---|---|---|
| Cheng-Yun Hsieh | National Taiwan University | James Chien-Mo Li |
| Francesco Angione | Politecnico di Torino | Paolo Bernardi, Riccardfo Cantoro |
| Jonti Talukdar | Arizona State University | Krishnendu Chakrabarty |
| Abdullah Giray Yağlıkçı | ETH Zurich | Onur Mutlu |
| Soyed Tuhin Ahmed | Karlsruhe Institute of Technology | Mehdi B. Tahoori |
| Mohammad Ebrahimabadi | University of Maryland Baltimore County | Naghmeh Karimi |
| Ferhat Can Ataman | Arizona State University | Sule Ozev |
14:15
Panel Title: HPC on Wheels: The role of test and reliability in future of automotive
Moderator: Andre Ivanov (U. British Columbia)
Panelists:
- Yervant Zorian (Synopsys)
- Nir Maor (Qualcomm)
- Mehdi Tahoori (imec / Karlsruhe Institute of Technology)
- Umit Ogras (University of Wisconsin-Madison)
15:45
Regular Session 8: Hardware Security - 2 (MU 242 La Paz)
Garblet: Multi-party Computation for Protecting Chiplet-based Systems
Speaker: Dev Mehta (WPI)
Authors: Mohammad HASHEMI (Worcester Polytechnic Institute (WPI)), Shahin TAJIK, Fatemeh GANJI (Worcester Polytechnic Institute)
Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization with Device-Level Studies
Speaker: Haocong Luo (ETH Zurich)
Authors: Haocong LUO, Ismail YUKSEL, Ataberk OLGUN, Abdullah Giray YAGLIKCI, Onur MUTLU (ETH Zurich)
Session Organizer: Arindam SANYAL (ASU)
Self-Calibrating Voltage Reference
Speaker: InHee Lee (U. Pittsburgh)
Machine Learning-Based Calibration Techniques for ADCs: An Overview
Speaker: Tuan Pham (SUNY)
Machine-learning based Calibration of Time-Interleaved ADC
Speaker: Sumukh Bhanushali (ASU)
Compute-in-Memory Mosaic: Orchestrating Tiny CIM Array Collaborations for Flexible and Scalable Deep Learning
Speaker: Amit Trivedi (U. Illinois at Chicago)
IP Session 4: Frontiers in Diagnosis and Debug (MU 230 Pima)
Session Organizer: Suriyaprakash Natarajan, Siemens EDA
Making Scan Diagnostics Data Work for You: Building an Efficient and Available Production Diagnostics Infrastructure
Speaker: Saghir Shaikh, Intel
Diagnosis Simulation
Speaker: Wu-Tung Cheng, Siemens EDA
Closed-Chassis In-Field System Test and Debug for Highly Reliable and Available Systems
Speaker: Sankaran Menon, Ericsson
17:30–21:00
Social Event (Desert Botanical Garden)
- Buses depart ASU campus (Gammage Parking Lot) at 5:30 PM.
- Arrive at Desert Botanical Garden (DBG) by 5:45 PM.
- Explore garden and exhibits until 6:30 PM.
- Cocktail hour begins at Webster Auditorium at 6:30 PM.
- Buffet dinner served at 7:15 PM.
- Buses return to ASU campus at 9:30 PM.
08:30
Title Talk: From Innovation to Impact: Dual-Use Microelectronics Shaping the FutureG Ecosystem
Session Moderator: Jennifer Kitchen (Arizona State U.)
10:00
Regular Session 9: Yield and Reliability - 2 (MU 230 Pima)
Data-Efficient Prediction of Minimum Operating Voltage via Inter- and Intra-Wafer Variation Alignment
Speaker: Yuxuan Yin (UC Santa Barbara)
Authors: Yuxuan YIN (University of California, Santa Barbara), Rebecca CHEN, Chen HE (NXP Semiconductor), Peng LI (University of California, Santa Barbara)
Enhancing Metrology to E-test Correlation Model Accuracy through Process Expertise Integration
Speaker: Ching-Yi Chang (University of Texas at Dallas)
Authors:Ching-Yi CHANG, Matthew NIGH (UT Dallas), John CARULLI (GlobalFoundries), Yiorgos MAKRIS (UT Dallas)
Artificial Bee Colony Optimization to Accelerate High-Speed Serial I/O Tx Equalization
Speaker: Cesar A. Sanchez-Martinez (Intel Corporation)
Authors: Cesar SANCHEZ-MARTINEZ (Intel Corportation), Paulo LOPEZ-MEYER (Intel Corporation), Andres VIVEROS WACHER (intel)
Session Organizer: Naghmeh Karimi (U. Maryland Baltimore County)
A novel variant of Threshold Implementation with cost amortization
Speaker: Sylvain Guilley (Secure IC)
Security verification in the context of high order hardware masking
Speaker: Cedric Tavernie (Hensoldt France)
Using digital sensors to detect high-order attacks targeting masking-protected devices
Speaker: Naghmeh Karimi (U. Maryland Baltimore County)
IP Session 5: Test, Debug, and Repair for Chiplet-Based Designs (MU 228 Cochise)
Session Organizer: Anshuman Chandra, Siemens EDA
Testing Strategies for Data and Clock Interconnects in 3D ICs
Speaker: Esteban Garita Rodriguez, Intel
Interconnect Test and Repair Language (ITRL) for Chiplets and 3D IC Packages
Speaker: Anshuman Chandra, Siemens EDA
Test and Debug of Analog Circuits in Chiplet-Based Designs
Speaker: Pradipta Ghosh, Microsoft, Microsoft
11:00
Regular Session 10: Test and Verification (MU 230 Pima)
CEDHDC: Lightweight Concurrent Error Detection for Reliable Hyperdimensional Computing
Speaker: Mehdi Tahoori (Karlsruhe Institute of Technology)
Authors: Mahboobe SADEGHIPOURRUDSARI, vincent MEYERS (Karlsruher Institut für Technologie (KIT)), Mehdi TAHOORI (Karlsruhe Institute of Technology)
CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking
Speaker: Sudipta Paria (University of Florida)
Authors: Dinesh Reddy ANKIREDDY, Sudipta PARIA, Aritra DASGUPTA, SANDIP RAY, Swarup BHUNIA (University of Florida)
A Hierarchical Graph Based Intelligent Method for Test Point Insertion
Speaker: Zhiteng Chao (Institute of Computing Technology)
Authors: Zhiteng CHAO (ICT), Bin SUN, Hongqin LYU, Ge YU, Mingjun WANG (SKLP, ICT, CAS), Wenxing LI, Zizhen LIU (Institute of Computing Technology, Chinese Academy of Sciences), Jianan MU (SKLP, ICT, CAS), Shengwen LIANG, Jing YE (Institute of Computing Technology, Chinese Academy of Sciences), Xiaowei LI (Institute of Computing Technology, CAS), HUAWEI LI (Chinese Academy of Sciences)
Special Session 11: Security Verification (MU 242 La Paz)
Session Organizer: Kanad Basu (UT Dallas)
Symbolic Execution at Scale: Verifying Large Open-Source SoCs with Assertion and
Information Flow Analysis
Speaker: Cynthia Sturton
AI-guided Threat Modeling and Test Plan Generation for Hardware Security
Verification
Speaker: Farimah Farahmandi (U Florida)
Security Verification of Microelectronic Systems with Integrated AI Accelerators: Scope, Practice, and Challenges
Speaker: Sandip Ray
OpenAssert: Towards Secure Assertion Generation using Large Language Models
Speaker: Kanad Basu (UT Dallas)
IP Session 6: Industry RAS/SDC Innovative Practices: from Si IP to Mega Fleets (MU 228 Cochise)
Session Organizer: Fei Su
SoC Level innovations for RAS and SDC
Speaker: Yogesh Varma, Intel
GPU Systems RAS/SDC innovations
Speaker: John Holm, Nvidia
Large scale fleet level RAS handling
Speaker: Drew Walton/ Rama Bhimanadhuni, Microsoft
13:30
Special Session 12: RF Test and Built-in Test (MU 242 La Paz)
Session Organizer: Jennifer Kitchen (ASU)
A Multi-Step Algorithm to Increase Accuracy of mm-Wave BIST Using Periodic Structures
Speaker: Noah Rajbharti
Doing More with Less: Integration for 5G/6G GaN Power Amplifiers
Speaker: Bruce Green
IP Session 7: Security Verification and Secure Testing Solutions (MU 230 Pima)
Session Organizer: Sohrab Aftabjahani (Intel)
Secure Semiconductor Development Using Synopsys Security Verification Solutions
Speaker: Shylaja Sen, Synopsys
Scalable Security Verification Enabled by AI
Speaker: Jermey S. Lee (Caspia)
Hardware Root of Trust for DFT
Speaker: Janusz Rajski, Siemens EDA
Emerging CAD solutions for side channel and fault injection analysis
Speaker: Lang Lin, Ansys
Special Session 13: SLM for Chiplets and Multi-Die Systems (MU 228 Cochise)
Session Organizer: Gurgen Harutyunyan (Synopsys)
SLM for Multi-Die Systems: Challenges and Opportunities
Speaker: Yervant Zorian (Synopsys)
Analysis of SRAM-based Register Files in GPUs and AI Accelerators
Speaker: Mehdi Tahoori (Karlsruhe Institute of Technology)
Combining DFX and Sensors to Combat Silent Data Corruption
Speaker: Amr Haggag (Arm)
14:30
Chiplet Architectures, Advanced Packaging, and the Importance of Test
Session Moderator: Arani Sinha (Intel)