IEEE VLSI Test Symposium 2020 (VIRTUAL CONFERENCE)

TTTC’s E. J. McCluskey Best Doctoral Thesis 2020 VT Semifinals winner.

After watching the student’s presentations and “virtually” meeting with them to ask questions the jury composed of:

  • Vivek Chickermane (Cadence)
  • Adit Singh (Auburn University)
  • Sohrab Aftabjahani (Intel Corp.)

has decreed that the top three students are:

  • Mohammad Nasim Imtiaz Khan, Penn. State Univ.
  • Georgios Volanis, Univ. Texas at Dallas
  • Gaurav Rajavendra Reddy, Univ. Texas at Dallas

Congratulations to Mohammad Nasim for winning the competition and thanks to all students and to the juries for the participation to the contest. Thanks to the effort you significantly contributed to make this virtual edition of VTS more attractive for the audience.

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Welcome from the chairs

On behalf of the whole VTS 2020 organizing committee:

L. Anghel – TIMA (General Chair)

A. Majumdar – Xilinx (General Chair)

S. Di Carlo – P. di Torino (Program Chair)

P. Song – IBM (Program Chair)

 

would like to welcome you to VTS 2020 virtual conference


Due to COVID-19 we have been forced to turn VTS 2020 into a virtual conference. However, even if we miss the pleasure of the face to face interaction, thanks to the whole VTS community, we have been able to build and incredible rich program that you can see below.

Access to the program requires a valid registration. Registrations are now closed (thanks to all participants for supporting the conference). Registered users will have access for a period of 10 months to:

  • Full formal proceedings
  • Video presentations of all papers and sessions
  • Discussion using a dedicated forum

Plenary talks

Regular papers

RP1 – Regular Session: ATPG & Compression

RP2 – Regular Session: Test, Reliability and Security in Emerging Application Domains

RP3 – Regular Session: Emerging Technologies Test and Reliability

RP4 – Regular Session: Hardware Security 1

RP5 – Regular Session: Machine Learning for Testing

RP6 – Regular Session: Defect/Fault Tolerance/Reliability

RP7 – Regular Session: Fault Modeling and Simulation

RP8 – Regular Session: SoC and SiP Test

RP9 – Regular Session: Hardware Security 2

RP10 – Regular Session: ATE and BIST

RP11 – Regular Session: CTC Best Papers

Special Sessions

Organizer: Ujjwal Guin (Auburn University)
 
 Abstract: Logic locking is a widely accepted technique to provide protection against the manufacturing of integrated circuits (ICs) towards zero trust. The underlying principle in logic locking is to incorporate additional key gates in the original netlist to obtain a key-dependent circuit. The original functionality of the chip is recovered only upon programming the correct key; otherwise, it produces incorrect results. Along with the development of different countermeasures, researchers have also proposed various attacks. Amongst the many, the Boolean Satisfiability (SAT) attack gained significant attention from the researchers. Consequentially, SAT resiliency becomes an important parameter to define the security of new locking techniques. However, an untrusted foundry may have more effective means to attack locking techniques without performing SAT analysis. This session will have talks related to the new direction of attacks on logic locking techniques that do not rely on traditional SAT analysis and explores new feasible attack and defense strategies.

Organizer: S. Ozev (Arizona State University)
 
Abstract: About 15% of the world’s population lives with a disability according to the annual world report on disability. Moreover, 100 to 190 million individuals face significant difficulties in functioning. Wearable sensors and mobile health applications are emerging as attractive solutions to augment clinical treatment and enable telepathic diagnostics. However, the success of these solutions depend critically on addressing a range of adaptation and technology challenges that have prevented the widespread use of wearable technology so far. This embedded tutorial will present these design and text solutions, and discuss potential solutions.

Organizers: Said Hamdioui (TU Delft), Mehdi Tahoori (Karlsruhe Institute of Technology)
 Abstract: STT-MRAM, ReRAM and PCM are the most promising non-volatile memory technologies offering many advantages and may enable many potential applications (e.g. as Internet-of-Things (IoT), automotive, aerospace, and last-level caches) . Therefore, these technology have received a large amount of attention for commercialization from major semiconductor companies such as SK hynix , Samsung, and Intel, etc. To enable mass production, high-quality yet cost-efficient manufacturing test solutions are crucial to ensure the required quality of products being shipped to end customers. The manufacturing process of such technologies involves not only conventional CMOS process but also additional fabrication and integration steps. The latter may lead to new defects that may cause new faults that were never observed by traditional memories. Hence, a blind application of conventional tests for existing memories such as SRAMs and DRAMs to emerging memories may lead to test escapes and/or yield loss.
This session aims at discussing the test of emerging memories. It will highlight the difference in testing emerging memories as compared with traditional ones, discusses the failure mechanisms, appropriate fault models and test solution.

Organizers: Said Hamdioui (TU Delft), Maksim Jenihhin (Tal Tech), Matteo Sonza Reorda (Politecnico di Torino)
 Abstract: Autonomous and Semi-Autonomous Vehicles applications, where a system failure could cause life-threatening situations, raise several challenges concerning Reliability, Security, Quality, and compliance to Safety Standards. New techniques and methodologies are required, able to facilitate and automate the development, verification and test of these applications. A new generation of EDA tools is also coming in order to support designers and safety/security experts in their jobs, while new standards are introduced to guide and constraint the design of new systems. In order to assess the quality of the proposed solutions, it is necessary to compare the results against what is applied in the industry. Nowadays, development life-cycles and verification techniques applied by industry are not disclosed, and each big player in the automotive sector has its own methodologies and tools. In addition, automotive hardware and software solutions are often not openly available to researchers, that are not able to verify their work on representative designs or assess the quality of their results. For that reason, there is a high demand for a suite of open-source benchmarks that would enable research on the different aspects of high-dependability automotive applications. It should be outlined that the benchmarks should include not only the plain hardware description (at different levels of abstraction), but also some versions including safety and security mechanisms, as well as software modules (Operating System, peripheral drivers, sample applications) running on the SoC. The goal of the special session is to summarize to the VTS audience the basic needs and requirements for such a benchmark suite by different companies working in the area (semiconductor, IP core, EDA companies) and to present a first version of the AutoSoC benchmark suite, developed within the frame of the RESCUE European project following the constraints and requirements listed above, together with some preliminary results related to test and safety.

Organizer: Ujjwal Guin (Auburn University)
 Abstract:The recent advancement of quantum computers poses a serious threat to the existing cryptographic algorithms. For example, RSA can be broken using “Shor’s algorithm”, which can factorize large integer numbers in polynomial time. To address the threat from the emergence of quantum computers, researchers are developing post-quantum cryptography (PQC) algorithms. The National Institute of Standard and Test (NIST) has also started a process of standardizing various PQC algorithms. This special session focuses on presenting efficient PQC algorithms, their implementation details, and challenges.

Organizer: Spencer Millican (Auburn University)
 Abstract: This embedded tutorial presents a history of test point (TP) architectures and test point insertion (TPI) methods for increasing pseudo-random and logic built-in self-test (LBIST) fault coverage. The history of TPI approaches is reviewed, including TPI for increasing stuck-at fault coverage, compressing test patterns, detecting path delay faults, and reducing test power. Known weaknesses of TPs are also explored, as are the future methods proposed to overcome these disadvantages.
Organizer: Marc Hutner (Teradyne)
 Abstract: Chiplet-based designs enable the heterogeneous integration of die from multiple process nodes into a single packaged product. High-bandwidth memory is a well-known high-volume chiplet-based product. Today, most chiplet-based logic products are single-vendor products built with proprietary die-to-die interfaces between the chiplets in a package. Industry and academia have developed standards and methods to address the test challenges expected with chiplet-based products. These efforts have focused on improving die yield and test access structures. The Open Compute Project’s Open Domain-Specific Architecture (ODSA) is a new effort that aims to define an open physical and logical D2D interface and create a marketplace of chiplets. With an open interface, product developers can integrate best in class chiplets from multiple vendors. An open D2D interface offers both new opportunities and challenges in testing multi-chiplet products. The opportunity is in leveraging economies of scale. The challenge is in enabling greater interoperability between test structures in different chiplets and across vendors. This paper reviews recent developments in chiplet test, especially leveraging work on HBM and discusses their extension to testing products based on open D2D interfaces.

IP Sessions

Organizer: Gurgen Harutyunyan (Synopsys)
 Abstract: Automotive continues its tremendous rise and remains to be the one of semiconductor market leaders. The main reasons of such underwhelming increase in automotive segment are in virtue of ever-lasting growing demands in functional safety, reliability, and security. There is a great deal of research being conducted now towards finding efficient test solutions for production mode to decrease DPPM/DPPB and investigating the types of tests that are most valuable for power-up/power-off mode, such as testing for aging faults, checking the checkers and etc. However, it is not really clear how much online and periodic tests are required during mission mode. In this session the presenters will share their perspectives on online checking and in-system test requirements for automotive applications.

Organizer: Haruo Kobayashi (Gunma University) and Kazumi Hatayama (EVALUTO Corporation)
 Abstract: The IP session highlights three innovative test practices in Asia, which include a testing solution for the millimeter- wave (76- to 81- GHz) without expensive instruments, an on-chip delay measurement method for in-field test and a power control method of at-speed scan test for IR violation reduction. These would be useful for automotive and IoT application device testing.

Organizer: Mike Ricchetti (Synopsis)
 Abstract: This Special Session provides updates on new and upcoming IEEE Test and Debug Standards. This includes an update on work to revise the 1500 Core Test standard, availability of IEEE 1838 — a newly published standard for 3DIC Test, and a report on the activities of a Study Group that is proposing a new IEEE Working Group to standardize state dump and state extraction for debug.

Organizers: Clark Liu (Powertech Technology Inc.) and Andrew Huang (NXP Semiconductor Taiwan Ltd.)
 Abstract: Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session address an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

Organizers: Abhijit Sathaye and Suriyaprakash Natarajan (Intel Corporation)
 Abstract: .
Organizers: Sohrab Aftabjahani and Suriyaprakash Natarajan (Intel Corporation)
 Abstract: As continuously many more aspects of our lives rely on increasingly connected and complex computing systems, the need for their robust operation has become essential. Their robustness requires their reliable operation, which can be susceptible to malicious attacks if exploitable vulnerabilities exists in them. Hence, there is a big demand for Design for Security (DFS) and Security Assurance and Validation (SAV) methods as well as CAD tools to create secure systems in an economical, fast, and scalable fashion. Moreover, current design CAD tools have the potential to weaken the security of designs or make them insecure as the result of design optimizations for power, performance, and timing. Therefore, creating an ecosystem of security-aware design, DFS, and SAV tools is of utmost importance as we have stepped into the security-essential computing-systems era to be able to incorporate the required security posture as the related parameter(s) into design, validation, and optimization processes. This session brings three experts from semiconductor and EDA industries together to share their perspectives regarding CAD for Security tools and methodologies at the present and in the future.
Organizer: Marc Hutner (Teradyne)
 Abstract: Chip density continues to grow  while general purpose IOs (GPIOs) are replaced by high speed serial IOs (HSIOs). Re-using HSIOs for scan test will therefore soon be essential to avoid an explosion in test time. Today, the industry is at a crossroads, as embarking on this journey raises many fundamental questions. A complete solution will also require support from multiple stakeholders. This presentation explains how an approach based on the IEEE 1149.10 and 1450 standards and existing ATE hardware is the best way to address the scan test bandwidth challenge while meeting the many requirement ranging from minimal design impact, test quality, and effective test bring-up. Our proposed end-to-end solution is being developed through collaboration with semiconductor companies, ATE manufacturers,  and test program generation software vendors to ensure that HSIO based scan test can be brought into the mainstream.

Students activities