IEEE VLSI Test Symposium 2017

The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, debug and repair of microelectronic circuits and systems.

The VTS Program Committee invites original, unpublished paper submissions for VTS 2017. Paper submissions should be complete manuscripts, up to six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: author name(s) and affiliation(s), and the mailing address, phone number, and e-mail address of the contact author. A 50-word abstract and five keywords identifying the topic area are also required.

YiorgosMakris
GENERAL CHAIR
Yiorgos Makris
University of Texas at Dallas – USA
Email: yiorgos.makris@utdallas.edu

ShrivatsRavi
PROGRAM CO-CHAIR
Srivaths Ravi
Texas Instruments
Email: srivaths.ravi@ti.com

avatarmale
PROGRAM CO-CHAIR
Amit Majumdar
Xilinx
Email: amit.majumdar@xilinx.com

VTS TOPICS

  • Analog/Mixed-Signal/RF Test 
  • ATPG & Compression
  • ATE Architecture & Software
  • Automotive Test & Safety
  • Built-In Self-Test (BIST)
  • Defect & Current Based Test
  • Defect/Fault Tolerance
  • Delay & Performance Test
  • Design for Testability (DFT)
  • Design Verification/Validation
  • Embedded System & Board Test
  • Embedded Test Methods
  • Emerging Technologies Test
  • FPGA Test
  • Fault Modeling and Simulation
  • Hardware Security
  • Low-Power IC Test
  • Microsystems/MEMS/Sensors Test
  • Memory Test and Repair
  • On-Line Test & Error Correction
  • Power/Thermal Issues in Test
  • System-on-Chip (SOC) Test
  • Test Standards
  • Test Economics
  • Test of Biomedical Devices
  • Test of High-Speed I/O
  • Test Quality and Reliability
  • Test Resource Partitioning
  • Transients and Soft Errors
  • 2.5D, 3D and SiP Test