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GENERAL INFO
SUBMISSIONS
PRACTICAL INFO
PROGRAM
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Tutorials |
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VLSI Test Symposium 2012 in co-operation with TTEP is happy to announce two half-a-day tutorials this year. The tutorials will held on Thursday April 17th. Details of the tutorial are indicated below.
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Tutorial 1: April 17th, 8:30AM-12:00PM (Hans Kornell) |
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Beyond DFT: The Convergence of DFM, Variability, Yield and Test
PRESENTER: Srikanth Venkataraman, Intel
ABSTRACT:
The tutorial goal is to show how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we conventionally think of as test. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. The basics of yield and what fabs do to improve defectivity and manage yield are described. DFM techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield are discussed. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered. This tutorial will provide background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs.
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Tutorial 2: April 17th, 1:00PM-4:30PM (Hans Kornell) |
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Hardware Security and Test
PRESENTERS: Ozgur Sinanoglu, New York University Abu Dhabi; Miodrag Potkonjak, University of California, Los Angeles; Peilin Song, IBM TJ Watson
ABSTRACT:
Globalization of Integrated Circuit (IC) design is making IC/Intellectual Property (IP) designers and users re-assess their trust in hardware. As the IC design flow spans the globe, driven by cost-conscious consumer electronics, hardware is increasingly prone to new kinds of attacks such as counterfeiting, hardware Trojans, side channel analysis, reverse engineering and IP piracy. An attacker, anywhere within this design flow, can reverse engineer the functionality of an IC/IP, steal and claim ownership of the IP, inject malicious circuitry (i.e., hardware Ttojans) into the IC, or introduce counterfeits into the supply chain. Moreover, an untrusted IC fab may overbuild ICs and sell them illegally. The semiconductor industry loses $4 billion annually due to some of these attacks.
In this tutorial, we expose the vulnerabilities of today's globalized IC design and manufacturing flow, review the emerging security threats, show that we can adapt techniques from VLSI testing to cope with these threats, and review a few recently developed design-for-trust techniques. We also provide a brief survey of process variation and device aging with an emphasis on current technologies and pending trends, and elaborate on the ramifications of process variation, device aging, and gate level characterization on several security tasks including resilience against timing, electromagnetic, and power attacks, malicious circuitry detection, diagnosis, and masking, IC counterfeiting detection, and the creation of hardware security primitives, such as physical unclonable functions (PUFs), public PUFs, and random number generators. Finally, we review the ongoing hardware security efforts at IBM TJ Watson Research Labs, and focus on a non-destructive method based on the detection of intrinsic light emission emitted from the powered-on FETs, to detect chip alterations.
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DEADLINES
Abstract: Oct. 18th '13
Final PDF: Oct. th '25 (Extended)
Notif.: Dec. 20th '13
CameraReady: Feb. 7th '14
PhD Contest: Mar. 9th '14 (Extended)
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