 |
Outstanding presentations and panels are specially recognized.
Each year, VTS has presented a Best Paper Award and, more recently, a
Best Panel Award as well, based on the evaluations of reviewers,
attendees, and an invited panel of judges.
Moreover, At VTS 2003, a TTEP 2000 Best Tutorial Award was granted to both:
- R.G. Bennetts, for his tutorial on "Boundary Scan and other 1149.X Standards"
- Gordon W. Roberts, for his tutorial on "Metrics, Techniques and New Developments in Mixed-Signal Testing"
| Year |
Best Paper |
Best Panel |
| 2002 |
Program Slicing for Hierarchical Test Generation
V. M. Vedula and J. A. Abraham
Yield-Reliability Modeling: Expermimental Verification and
Application to Burn-In Reduction
T. S. Barnett, A. D. Singh, M. Grady, and K. Purdy
|
Debating the Future of Burn-In
Organizer: S. Mitra -- Moderator: E.J. McCluskey
|
| 2000 |
A Technique for Logic Fault Diagnosis of Interconnect Open Defects
S. Venkataraman and S. B. Drummonds
|
|
| 1999 |
REDO - Random Excitation and Deterministic Observation -
First Commercial Experiment
M.R. Grimaila, S. Lee, J. Dworak, K.M. Butler, H. Balachandran, B. Houchins,
V. Mathur, J. Park, L.C. Wang and M.R. Mercer
|
Does Failure Analysis and Silicon Debug Research Need to be Redirected?
Moderator: A. Majumdar -- Coordinator: S. Chakravarty
Panelists: M. Abramovici, R. Aitken, K. Fuchs, C. Landrault,
S. Venkataraman, S. Pabisetty, S. Narayanan
|
| 1998 |
Nonlinear Analog DC Fault Simulation by One-Step Relaxation
M.W. Tian and CJ R. Shi
Design of Phase Shifters for BIST Applications
J. Rajski and J. Tyszer
|
Open Microphone: Can ATE Handle Next Generation Designs
Moderator: Ed McCluskey
|
| 1997 |
SPITFIRE: Scalable Parallel Algorithms for Test Set Partitioned Fault Simulation
D. Krishnaswamy, E.M. Rudnick, J.H. Patel, and P. Banerjee
|
Will 0.1um Digital Circuits Require Mixed-Signal Testing
Moderator: S. Sunter-- Coordinator: M. Soma
Panelists: M. Breuer, B. Kaminska, J. McDermid, V. Rayapathi, D. Wheater
|
| 1996 |
Full Fault Dictionary Storage Based on Labeled Tree Encoding
V. Boppana, I. Hartanto, and W.K. Fuchs
|
Delay Fault Testing: How Robust are our Models?
Moderator: TW Williams -- Coordinators: M. Abramovici and A. Chatterjee
Panelists: K.T. Chen, S. Gupta, S. Pilarski, J. Savir, P. Varma
|
| 1995 |
Arithmetic Built-In Self Test for High-Level Synthesis
N. Mukherjee, M. Kassab, J. Tyszer, and J. Rajski
|
|
| 1994 |
Structural Constraints for Circular Self-Test Paths
J. Carletta and C. Papachristou
|
|
| 1993 |
Design SRAMs for Burn-In
W. Reohr, Y. Chan, D. Plass, A. Pelella, and P. Wu
|
|
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