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GENERAL INFO
THE SYMPOSIUM
PROGRAM
SUBMISSIONS
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VTS - Apr 30th-May 4th, 2006 |
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VTS EXPLORES EMERGING TRENDS AND NOVEL CONCEPTS IN TESTING,
VERIFICATION/VALIDATION OF MICROELECTRONIC CIRCUITS AND SYSTEMS
VTS was organized in 1982 specifically to focus attention on newly developing test technology,
particularly ATPG and Design for Test tools and methods. Since then, it has grown to include
tutorials, panels, and innovative practices. VTS enjoys the participation of attendees from all
over the world, and each year solicits new contributions in areas of current interest to the
semiconductor test community.
Today, the VTS Program Committee annually invites original, unpublished paper submissions.
Proposals regarding innovative practices and special sessions are also solicited.
Innovative practice presentations highlight cutting-edge challenges faced by test practitioners,
and innovative solutions employed to address them. Special sessions include, for example, panels,
embedded tutorials, or hot topic presentations as they might emerge from year to year.
For further information:
| Technical Paper Submissions |
General Information |
PROGRAM CHAIR
Paolo Prinetto
Politicnico di Torino
Dip. di Automatica e Informatica
Corso Duca degli Abruzzi 24
I-10129 Torino TO, Italy
T: +39-011-564-7007
E:Paolo.Prinetto@Polito.it
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GENERAL CHAIR
Irith Pomeranz
Purdue University
School of ECE
EE Bldg.
West Lafayette, IN 47907, USA
T: +1-765-494-3357
E: pomeranz@ecn.purdue.edu
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Corporate Support |
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VTS is supported each year by several leading companies from the test,
semiconductor, and EDA industries. If you would like to become a
corporate supporter of VTS 2006,
please contact the General Chair Irith Pomeranz
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VTS Topics |
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Major topics include, but are not limited to:
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Analog, M-S & RF Test
Automatic Test Generation
ATE Architecture & SW
Board & System Test
Built-In Self-Test (BIST)
Current Based Test
Defect Tolerance
Delay & Performance Test
Design for Testability (DFT)
Design Verification/Validation
Diagnosis and Debug
Embedded System Test
Embedded Test Methods
Fault Modeling and Simulation
Infrastructure IP
MEMS Test
Memory Test and Repair
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Microprocessor Test
Multi-Chip Module Test
Nanometer Technologies Test
On-Line Test
Power Issues in Test
Self-Repair & Fault Tolerance
System-on-Chip (SOC) Test
System-in-Package Test
Test Resource Partitioning
Thermal Test
Test Data Compression
Test of High-Speed I/O
Test Quality and Reliability
Test Resource Partitioning
Transients and Soft Errors
Yield Analysis & Optimization
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LOCATION
VTS will take place from April 30th to May 4th, 2006 in Claremont Resort, Berkeley, California, USA More...
DEADLINES
Submission: Oct. 7th '05 Notification: Jan. 6th '06 Camera R.: Feb. 10th '06
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CONTACTS & FEEDBACK
For any questions you can contact the
VTS Office,
the General Chair or the
Program Chair.
Moreover, The VTS Organizing Committee is interested in providing a rich
historical view of VTS. Please send information you believe to be relevant
to the historian.
For questions related to this website, please contact the
Webmaster
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